Output Delay Measurement Methodology

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English

Output delays are measured with short output traces. Standard termination was used for all testing. The propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 1 and Figure 2.

Figure 1. Single-Ended Test Setup

Figure 2. Differential Test Setup

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using this method:

  1. Simulate the output driver of choice into the generalized test setup using values from Table 1.
  2. Record the time to VMEAS.
  3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load.
  4. Record the time to VMEAS.
  5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
Table 1. Output Delay Measurement Methodology
Description I/O Standard Attribute RREF (Ω) CREF 1 (pF) VMEAS (V) VREF (V)
LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0
LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0
LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0
LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0
LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0
LVTTL, 3.3V LVTTL 1M 0 1.65 0
LVDCI, HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 50 0 VREF 0.75
LVDCI, HSLVDCI, 1.8V LVDCI_15, HSLVDCI_18 50 0 VREF 0.9
HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 50 0 VREF 0.6
HSTL, class I, 1.5V HSTL_I 50 0 VREF 0.75
HSTL, class I, 1.8V HSTL_I_18 50 0 VREF 0.9
HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 VREF 0.6
SSTL12 (stub series terminated logic), 1.2V SSTL12 50 0 VREF 0.6
SSTL135 and SSTL135 class II, 1.35V SSTL135, SSTL135_II 50 0 VREF 0.675
SSTL15 and SSTL15 class II, 1.5V SSTL15, SSTL15_II 50 0 VREF 0.75
SSTL18, class I and class II, 1.8V SSTL18_I, SSTL18_II 50 0 VREF 0.9
POD10, 1.0V POD10 50 0 VREF 1.0
POD12, 1.2V POD12 50 0 VREF 1.2
DIFF_HSTL, class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6
DIFF_HSTL, class I, 1.5V DIFF_HSTL_I 50 0 VREF 0.75
DIFF_HSTL, class I, 1.8V DIFF_HSTL_I_18 50 0 VREF 0.9
DIFF_HSUL, 1.2V DIFF_HSUL_12 50 0 VREF 0.6
DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6
DIFF_SSTL135 and DIFF_SSTL135 class II, 1.35V DIFF_SSTL135, DIFF_SSTL135_II 50 0 VREF 0.675
DIFF_SSTL15 and DIFF_SSTL15 class II, 1.5V DIFF_SSTL15, DIFF_SSTL15_II 50 0 VREF 0.75
DIFF_SSTL18, class I and II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9
DIFF_POD10, 1.0V DIFF_POD10 50 0 VREF 1.0
DIFF_POD12, 1.2V DIFF_POD12 50 0 VREF 1.2
LVDS (low-voltage differential signaling), 1.8V LVDS 100 0 0 2 0
SUB_LVDS, 1.8V SUB_LVDS 100 0 0 2 0
MIPI D-PHY (high speed) 1.2V MIPI_DPHY_DCI_HS 100 0 0 2 0
MIPI D-PHY (low power) 1.2V MIPI_DPHY_DCI_LP 1M 0 0.6 0
  1. CREF is the capacitance of the probe, nominally 0 pF.
  2. The value given is the differential output voltage.