PLL Switching Characteristics

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID
DS931
Release Date
2022-04-13
Revision
1.2 English
Table 1. PLL Specification
Symbol Description 1 Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
PLL_FINMAX Maximum input clock frequency 933 800 800 MHz
PLL_FINMIN Minimum input clock frequency 70 70 70 MHz
PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max
PLL_FINDUTY Input duty cycle range: 70–399 MHz 35–65 %
Input duty cycle range: 400–499 MHz 40–60 %
Input duty cycle range: >500 MHz 45–55 %
PLL_FVCOMIN Minimum PLL VCO frequency 750 750 750 MHz
PLL_FVCOMAX Maximum PLL VCO frequency 1500 1500 1500 MHz
PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs 2 0.12 0.12 0.12 ns
PLL_TOUTJITTER PLL output jitter. Note 3
PLL_TOUTDUTY PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B duty-cycle precision 4 0.20 0.20 0.20 ns
PLL_TLOCKMAX PLL maximum lock time 100 µs
PLL_FOUTMAX PLL maximum output frequency at CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B 775 667 667 MHz
PLL maximum output frequency at CLKOUTPHY 2667 2400 2133 MHz
PLL_FOUTMIN PLL minimum output frequency at CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B 5 5.86 5.86 5.86 MHz
PLL minimum output frequency at CLKOUTPHY 2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode: 375 MHz
PLL_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 ns
PLL_FPFDMAX Maximum frequency at the phase frequency detector 667.5 667.5 667.5 MHz
PLL_FPFDMIN Minimum frequency at the phase frequency detector 70 70 70 MHz
PLL_FBANDWIDTH PLL bandwidth at typical 14 14 14 MHz

PLL_FDPRCLK_MAX

Maximum DRP clock frequency 250 250 250 MHz
  1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies.
  2. The static offset is measured between any PLL outputs with identical phase.
  3. Values for this parameter are available in the Clocking Wizard.
  4. Includes global clock buffer.
  5. Calculated as FVCO/128 assuming output duty cycle is 50%.