Speed Grade Designations

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)

Document ID

DS931

Release Date

2022-09-06

Revision

1.3 English

Because individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 1 correlates the current status of the Artix UltraScale+ FPGAs on a per speed grade basis.

Table 1. Speed Grade Designations by Device
Device	Speed Grade, Temperature Ranges, and V_CCINT Operating Voltages
Device	Advance	Preliminary	Production
XCAU10P			-2E (V_CCINT = 0.85V), -2I (V_CCINT = 0.85V) -1E (V_CCINT = 0.85V), -1I (V_CCINT = 0.85V) -1LI (V_CCINT = 0.85V)¹ -1LI (V_CCINT = 0.72V)¹
XCAU15P			-2E (V_CCINT = 0.85V), -2I (V_CCINT = 0.85V) -1E (V_CCINT = 0.85V), -1I (V_CCINT = 0.85V) -1LI (V_CCINT = 0.85V)¹ -1LI (V_CCINT = 0.72V)¹
XCAU20P			-2E (V_CCINT = 0.85V), -2I (V_CCINT = 0.85V) -1E (V_CCINT = 0.85V), -1I (V_CCINT = 0.85V) -1LI (V_CCINT = 0.85V)¹ -1LI (V_CCINT = 0.72V)¹
XCAU25P			-2E (V_CCINT = 0.85V), -2I (V_CCINT = 0.85V) -1E (V_CCINT = 0.85V), -1I (V_CCINT = 0.85V) -1LI (V_CCINT = 0.85V)¹ -1LI (V_CCINT = 0.72V)¹
The lowest power -1L devices, where V_CCINT = 0.72V, are listed in the Vivado Design Suite as -1LV. Otherwise, the -1L devices, where V_CCINT = 0.85V, are listed in the Vivado Design Suite as -1L.