Device Pin-to-Pin Input Parameter Guidelines

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

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The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With MMCM (Internal Mode)
Symbol Description Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TSUMMCM_VM1102 Global clock input and input flip-flop (or latch) with MMCM Setup XCVM1102 N/A           ns
THMMCM_VM1102 Hold N/A           ns
TSUMMCM_VM1302 Setup XCVM1302 N/A –0.61 –0.64 –0.64 –0.59 –0.59 ns
THMMCM_VM1302 Hold N/A 3.61 4.17 4.30 4.17 4.33 ns
TSUMMCM_VM1402 Setup XCVM1402 N/A –0.49 –0.51 –0.51 –0.46 –0.46 ns
THMMCM_VM1402 Hold N/A 3.97 4.56 4.69 4.56 4.72 ns
TSUMMCM_VM1502 Setup XCVM1502 N/A –0.77 –0.77 –0.77 –0.74 –0.74 ns
THMMCM_VM1502 Hold N/A 3.82 4.20 4.35 4.26 4.43 ns
TSUMMCM_VM1802 Setup XCVM1802 N/A –0.88 –0.95 –0.95 –0.91 –0.91 ns
THMMCM_VM1802 Hold N/A 4.16 4.80 4.98 4.81 5.01 ns
TSUMMCM_XQ_VM1802 Setup XQVM1802 N/A N/A –0.95 –0.95 N/A –0.91 ns
THMMCM_XQ_VM1802 Hold N/A N/A 4.80 4.98 N/A 5.01 ns
TSUMMCM_VM2202 Setup XCVM2202   N/A         ns
THMMCM_VM2202 Hold   N/A         ns
TSUMMCM_VM2302 Setup XCVM2302   N/A         ns
THMMCM_VM2302 Hold   N/A         ns
TSUMMCM_VM2502 Setup XCVM2502   N/A         ns
THMMCM_VM2502 Hold   N/A         ns
TSUMMCM_VM2902 Setup XCVM2902   N/A         ns
THMMCM_VM2902 Hold   N/A         ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.