Device Pin-to-Pin Input Parameter Guidelines

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID

DS956

Release Date

2022-08-02

Revision

1.5 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With MMCM (Internal Mode)
Symbol	Description		Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)						Units
				0.88V (H)		0.80V (M)		0.70V (L)
				-3	-2	-2	-1	-2	-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^{1, 2, 3}
T_{SUMMCM_VM1102}	Global clock input and input flip-flop (or latch) with MMCM	Setup	XCVM1102	N/A						ns
T_{HMMCM_VM1102}		Hold	XCVM1102	N/A						ns
T_{SUMMCM_VM1302}		Setup	XCVM1302	N/A	–0.61	–0.64	–0.64	–0.59	–0.59	ns
T_{HMMCM_VM1302}		Hold	XCVM1302	N/A	3.61	4.17	4.30	4.17	4.33	ns
T_{SUMMCM_VM1402}		Setup	XCVM1402	N/A	–0.49	–0.51	–0.51	–0.46	–0.46	ns
T_{HMMCM_VM1402}		Hold	XCVM1402	N/A	3.97	4.56	4.69	4.56	4.72	ns
T_{SUMMCM_VM1502}		Setup	XCVM1502	N/A	–0.77	–0.77	–0.77	–0.74	–0.74	ns
T_{HMMCM_VM1502}		Hold	XCVM1502	N/A	3.82	4.20	4.35	4.26	4.43	ns
T_{SUMMCM_VM1802}		Setup	XCVM1802	N/A	–0.88	–0.95	–0.95	–0.91	–0.91	ns
T_{HMMCM_VM1802}		Hold	XCVM1802	N/A	4.16	4.80	4.98	4.81	5.01	ns
T_{SUMMCM_XQ_VM1802}		Setup	XQVM1802	N/A	N/A	–0.95	–0.95	N/A	–0.91	ns
T_{HMMCM_XQ_VM1802}		Hold	XQVM1802	N/A	N/A	4.80	4.98	N/A	5.01	ns
T_{SUMMCM_VM2202}		Setup	XCVM2202		N/A					ns
T_{HMMCM_VM2202}		Hold	XCVM2202		N/A					ns
T_{SUMMCM_VM2302}		Setup	XCVM2302		N/A					ns
T_{HMMCM_VM2302}		Hold	XCVM2302		N/A					ns
T_{SUMMCM_VM2502}		Setup	XCVM2502		N/A					ns
T_{HMMCM_VM2502}		Hold	XCVM2502		N/A					ns
T_{SUMMCM_VM2902}		Setup	XCVM2902		N/A					ns
T_{HMMCM_VM2902}		Hold	XCVM2902		N/A					ns
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. Use IBIS to determine any duty-cycle distortion incurred using various standards.