Device Pin-to-Pin Output Parameter Guidelines

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID

DS956

Release Date

2022-08-02

Revision

1.5 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol	Description^{1, 2}	Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)						Units
			0.88V (H)		0.80V (M)		0.70V (L)
			-3	-2	-2	-1	-2	-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
T_ICKOFMMCM	Global clock input and output flip-flop with MMCM	XCVM1102	N/A						ns
		XCVM1302	N/A	6.29	6.82	7.27	7.48	8.08	ns
		XCVM1402	N/A	7.24	7.85	8.32	8.52	9.12	ns
		XCVM1502	N/A	6.99	7.54	8.00	8.23	8.83	ns
		XCVM1802	N/A	7.34	8.05	8.54	8.71	9.35	ns
		XQVM1802	N/A	N/A	8.05	8.54	N/A	9.35	ns
		XCVM2202		N/A					ns
		XCVM2302		N/A					ns
		XCVM2502		N/A					ns
		XCVM2902		N/A					ns
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.