Versal Prime devices are powered by multiple power supply pins that must use specific rail combinations and power sequences. Only some combinations and sequences are supported. The combinations depend upon the selected device, speed specification, and power management options. The required sequencing and power delivery options are shown in the power design tab in the Xilinx® Power Estimator (XPE). For more information, see https://www.xilinx.com/power.
| Symbol | Description | Min | Max | Units |
|---|---|---|---|---|
| TVCCAUX | Ramp time from GND to 95% of VCCAUX | 0.2 | 40 | ms |
| TVCCAUX_PMC | Ramp time from GND to 95% of VCCAUX_PMC | 0.2 | 40 | ms |
| TVCCAUX_SMON | Ramp time from GND to 95% of VCCAUX_SMON | 0.2 | 40 | ms |
| TVCC_CPM5 | Ramp time from GND to 95% of VCC_CPM5 | 0.2 | 40 | ms |
| TVCC_FUSE | Ramp time from GND to 95% of VCC_FUSE | 0.2 | 40 | ms |
| TVCCINT | Ramp time from GND to 95% of VCCINT | 0.2 | 40 | ms |
| TVCCINT_GT | Ramp time from GND to 95% of VCCINT_GT | 0.2 | 40 | ms |
| TVCC_IO_VCC_SOC | Ramp time from GND to 95% of VCC_IO and VCC_SOC | 0.2 | 40 | ms |
| TVCCO | Ramp time from GND to 95% of VCCO | 0.2 | 40 | ms |
| TVCC_PMC | Ramp time from GND to 95% of VCC_PMC | 0.2 | 40 | ms |
| TVCC_PSFP | Ramp time from GND to 95% of VCC_PSFP | 0.2 | 40 | ms |
| TVCC_PSLP | Ramp time from GND to 95% of VCC_PSLP | 0.2 | 40 | ms |
| TVCC_RAM | Ramp time from GND to 95% of VCC_RAM | 0.2 | 40 | ms |
| TGTY_AVCC | Ramp time from GND to 95% of VGTY_AVCC | 0.2 | 40 | ms |
| TGTY_AVCCAUX | Ramp time from GND to 95% of VGTY_AVCCAUX | 0.2 | 40 | ms |
| TGTY_AVTT | Ramp time from GND to 95% of VGTY_AVTT | 0.2 | 40 | ms |
| TGTM_AVCC | Ramp time from GND to 95% of VGTM_AVCC | 0.2 | 40 | ms |
| TGTM_AVCCAUX | Ramp time from GND to 95% of VGTM_AVCCAUX | 0.2 | 40 | ms |
| TGTM_AVTT | Ramp time from GND to 95% of VGTM_AVTT | 0.2 | 40 | ms |