FAXI_CLK
|
Maximum AXI4 and ACE-LITE
interface frequency |
400 |
400 |
350 |
350 |
300 |
250
1
|
MHz |
FPLAT_CLK
|
Maximum PL address translation (AT) interface frequency |
400 |
400 |
350 |
350 |
300 |
250
2
|
MHz |
FPLATB_CLK
|
Maximum PL-PS advanced trace bus (ATB) interface
frequency |
400 |
400 |
350 |
350 |
300 |
250
2
|
MHz |
FPSACE_CLK
|
Maximum AXI4 coherency
extensions (ACE) interface frequency |
400 |
400 |
350 |
350 |
300 |
250
2
|
MHz |
FPSACP_CLK
|
Maximum accelerator coherency port (ACP) interface
frequency |
400 |
400 |
350 |
350 |
300 |
250
2
|
MHz |
FPSFCIDMA_CLK
|
Maximum DMA flow-control interface (FCI) frequency |
400 |
400 |
350 |
350 |
300 |
250
3
|
MHz |
- The -1LLI and -1LSI low-power
devices support an overdrive voltage where the maximum clock frequency is 280 MHz
for AXI4 (when VCC_PSFP = 0.88V or VCC_PSLP = 0.88V) and
ACE-LITE (when VCC_PSFP = 0.88V).
- The -1LLI and -1LSI low-power
devices support an overdrive voltage where the maximum clock frequency is 280 MHz
when VCC_PSFP = 0.88V.
- The -1LLI and -1LSI low-power
devices support an overdrive voltage where the maximum clock frequency is 280 MHz
when VCC_PSLP = 0.88V.
|