Revision History

The following table shows the revision history for this document.

Section	Revision Summary
8/02/2022 Version 1.5
General updates	Updated the Table 1 including production release of some of the devices/speed grade/operating voltages using the Vivado Design Suite 2022.1.1 v2.10 in Speed Grade Designations and Production Silicon and Software Status.
Speed Grade Designations	Moved the -2LLI (V_CCINT = 0.70V) speed file to Evaluation in some devices where it was listed as production. This speed file is not available in the software tools.
DC Characteristics Over Recommended Operating Conditions	Updated the I_{CC_BATT} conditions and values.
PMC SD/SDIO Controller Interface	Added T_SDDCK and T_SDCKD minimum values and updated the T_SDSDR12DCK minimum value.
PMC eMMC Controller Interface	Added T_EMMEDCK and T_EMMCCKD minimum values.
Device Pin-to-Pin Output Parameter Guidelines	Updated the XCVM1502 values and added the -2H values for XCVM1302, XCVM1402, and XCVM1802.
Device Pin-to-Pin Input Parameter Guidelines	Updated the XCVM1502 values and added the -2H values for XCVM1302, XCVM1402, and XCVM1802.
GTM Transceiver User Clock Switching Characteristics	Updated table values to match the maximum 58 Gb/s line rate.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM)	Clarified that Overdrive support is not available on -1L (0.70V) devices in Table 4, Table 5, and Table 6.
5/02/2022 Version 1.4
General updates	Added XQ devices: XQVM1102, XQVM1402, XQVM1502, and XQVM1802.
Absolute Maximum Ratings	Revised the V_{GTY_AVCC} maximums from 0.97V to 1.01V. Revised the GT transceivers V_IN specifications and added unpowered and powered values for V_{IN_DC} and V_{IN_AC}. Revised the transceiver reference clock absolute input AC and DC voltages. Removed duplicate I_DCIN-FLOAT rating and note. Removed note 9.
Available Speed Grades and Operating Voltages	Added the -1MSM speed grade for XQ devices (-1MP-m-S device code).
Power Supply Requirements	Updated the description.
AC Switching Characteristics	Updated the Table 1 including production release of some of the devices/speed grade/operating voltages using the Vivado Design Suite 2022.1 v2.06 in Speed Grade Designations and Production Silicon and Software Status.
Clocks and Reset	Added note 2 to Table 1.
PMC Octal-SPI Controller Interface	Added values to Table 1 and updated note 1.
PMC SD/SDIO Controller Interface	Added values to Table 1 and updated note 1.
PMC eMMC Controller Interface	Added values and notes 3 and 4 to Table 1 and updated note 1.
Memory Interface Controller	Added note 7 to Table 1
GTM Transceiver Specifications	Added GTM transceiver specifications. Some Versal Prime devices have GTM transceivers, see the Versal Architecture and Product Data Sheet: Overview (DS950).
GTY and GTYP Transceiver Performance	Added the -2H column. Some XC devices offer a -2HSI device and others offer a -3SE device. See the Speed and Temperature Grade table in the Versal Architecture and Product Data Sheet: Overview (DS950).
Programmable Logic Integrated Block for PCIe	Updated Table 2.
1/06/2022 Version 1.3
Summary and General Updates	Added the XCVM2202, XCVM2302 and removed XCVM2602 devices.
Summary and General Updates	Added the GTM transceiver, PCIe 5.0, and CPM5 specifications where applicable.
Absolute Maximum Ratings	Revised the maximum V_CCO from 3.465V to 3.63V for certain HDIO and PSIO banks.
	Added V_REF specifications.
	Removed T_SOL guidelines. See Versal ACAP Packaging and Pinouts Architecture Manual (AM013) for appropriate specifications by package type.
DC Characteristics Over Recommended Operating Conditions	Updated the HDIO, PSIO, and XPIO maximum capacitance and added Note 2.
Available Speed Grades and Operating Voltages	Added the Vivado Design Tools Device Code column.
AC Switching Characteristics	Updated to Vivado Design Suite 2021.2.1 v2.05 for XCVM1802 and v1.02 for XCVM1302, XCVM1402.
AC Switching Characteristics	Added the Evaluation Product Specification description.
Speed Grade Designations	Revised the available speed specifications by device.
Production Silicon and Software Status	Revised the production released version of the XCVM1802 to Vivado Design Suite 2021.2.1 v2.05 and added Note 4.
PS USB Controller Interface	Revised T_ULPICKD input hold time from 0 to 0.5 ns (500 ps).
Table 4	Added Note 4 limiting the RLDRAM3 maximum performance for -2L and -1L speed grades.
Device Pin-to-Pin Output Parameter Guidelines	Revised the XCVM1802 speed specification values for Vivado Design Suite 2021.2.1 v2.05 and added the Vivado Design Suite 2021.2.1 v1.02 values for XCVM1302 and XCVM1402.
Device Pin-to-Pin Input Parameter Guidelines	Revised the XCVM1802 speed specification values for Vivado Design Suite 2021.2.1 v2.05 and added the Vivado Design Suite 2021.2.1 v1.02 values for XCVM1302 and XCVM1402.
Package Parameter Guidelines	Added some XCVM1302 and XCVM1402 values.
7/01/2021 Version 1.2
Recommended Operating Conditions	Added Note 9.
AC Switching Characteristics	Updated the speed file versions to Vivado Design Suite 2021.1 v2.01.
Speed Grade Designations	Moved the XCVM1802 to production for the following speed grades: -2MSE, -2MLE, -2MSI, -2MLI (V_CCINT = 0.80V) -1MSE, -1MLE, -1MSI, -1MLI (V_CCINT = 0.80V)
Production Silicon and Software Status	Updated the software status for the following speed grades to Vivado Design Suite 2021.1 v2.01. -2MSE, -2MLE, -2MSI, -2MLI (V_CCINT = 0.80V) -1MSE, -1MLE, -1MSI, -1MLI (V_CCINT = 0.80V)
Processing System Performance Characteristics	In Table 1, updated F_RPUMAX for the -3/-2 (0.88V (H)) speed grades.
Processing System Performance Characteristics	Added F_{PLATB_CLK} to Table 2.
PS CAN FD Controller Interface	Added Note 2.
PS Trace Interface	Updated Note 2 and added Note 4.
Programmable Logic Performance Characteristics	Updated Table 3 for -2/-1 (0.80V (M) and 0.70V (L)) speed grades.
Programmable Logic Performance Characteristics	In Table 4: Removed Note 4: Maximum performance for interfaces using more than one bank. Added Note 1. Revised the -1 performance values for DRAM type DDR4 single rank component. Revised the -1M performance value for DRAM type 1 rank RDIMM, DIMM.
Accelerator RAM Switching Characteristics	Added the section because the accelerator RAM is available in the VM1102 device.
Device Pin-to-Pin Output Parameter Guidelines	Updated the T_ICKOFMMCM values to the speed specifications in Vivado Design Suite 2021.1.
Device Pin-to-Pin Input Parameter Guidelines	Updated the setup and hold values to the speed specifications in Vivado Design Suite 2021.1.
Memory Interface Controller	Added Note 1 to Table 1, and updated Note 5.
GTY and GTYP Transceiver Configuration Interface Port Switching Characteristics	Reduced the maximum GTYAPB3CLK frequency in Table 1.
GTY and GTYP Transceiver User Clock Switching Characteristics	Updated values in Table 2.
4/14/2021 Version 1.1
General	Added GTYP transceiver specifications.
Summary	Added V_{CC_PMC} overdrive support.
Table 1	Updated the notes.
Table 1	Revised maximum V_CCBATT, added minimum CFU reference clock frequency to F_{CFU_REFCLK}, added overdrive conditions to V_{CC_PMC} , added Notes 2, 3, 4, 8, 12, and updated Note 15.
Available Speed Grades and Operating Voltages	Updated table with standard and overdrive modes. Added Note 4.
Table 1	Added table.
VIN Maximum Allowed AC Voltage Overshoot and Undershoot	Added note 3 to Table 2.
Table 3	Updated V_IL maximum and V_IH minimum for LVSTL06_12 and LVSTL_11.
Table 8	Removed LVSTL_11 (V_OH = 33). Added Note 2.
Table 9	Removed LVSTL_11 (V_OH = 33).
LVDS DC Specifications (LVDS15)	Added V_{ICM_AC} and Note 5.
AC Switching Characteristics	Updated the speed file versions and the definitions for engineering sample, pre-production, and production product specification.
Speed Grade Designations	Moved the XCVM1802 to production for the following speed grades: -2LSE, -2LLE (V_CCINT = 0.70V) -1LSE, -1LLE, -1LSI, -1LLI (V_CCINT = 0.70V)
Production Silicon and Software Status	The XCVM1802 is production released using Vivado Design Suite 2020.3 v2.00.
Device Identification	Updated the IDCODE for the XCVM1802, and added notes to explain the table fields.
Processing System Performance Characteristics	Updated Table 1.
Processing System Performance Characteristics	Added F_{PSFCIDMA_CLK} and Note 3 to Table 2.
Clocks and Reset	Added T_MODEPOR, and T_PORMODE to Table 3.
	Added F_{FPD_LSBUS_CLK} and Note 1 to Table 4.
	Added F_{RPLL_TO_XPD_CLK}, F_{LPD_LSBUS_CLK}, F_{TS_REFCLK}, F_{PSM_REFCLK}, F_{DBG_LPD_CLK}, F_{USB_REFCLK}, F_{DBG_TS_CLK}, and Notes 1, 3, 4, and 6 to Table 5.
	In Table 6, updated the IRO tolerance range.
	In Table 7, added F_{EFUSE_REFCLK}, F_{SMON_REFCLK}, F_{NPI_REFCLK}, F_{PPLL_TO_XPD_CLK}, F_{NPLL_TO_XPD_CLK}, F_{LSBUS_REFCLK}, F_{AXI_TO_REFCLK}, F_{USB_SREFCLK}, and F_{HSM0_REFCLK}. Revised the -3 specifications for F_{PL0_REFCLK}, F_{PL1_REFCLK}, F_{PL2_REFCLK}, and F_{PL3_REFCLK}. Updated the Notes 1 and 4.
	Added Note 1 to Table 8.
PMC JTAG and SelectMAP	Extensive updates to Table 1 and Table 2.
PMC Quad-SPI Controller Interface	Extensive changes to the table. Updated Note 1 and added Note 2 and 5.
PMC Octal-SPI Controller Interface	Removed load condition column. Updated Note 1.
PS USB Controller Interface	Added T_ULPIDCK, T_ULPICKD, and T_ULPICKO.
PS Gigabit Ethernet MAC Controller Interface	Added F_GEMTSUREFCLK.
PS Trace Interface	Updated F_TCECLK and Note 3.
Network on Chip Switching Characteristics	Updated the performance values in the table.
Programmable Logic Performance Characteristics	Updated values in Table 1. Updated values in Table 2 and added Notes 3 and 4. Updated the values in Table 3. Updated the values in Table 4 and added Note 4: Maximum performance for interfaces using more than one bank. Removed the LVDS Native-Mode 1000BASE-X Support table.
Block RAM Switching Characteristics	Updated T_{RCKO_DO} and T_{RCKO_DO_REG}.
Input/Output Delay Switching Characteristics	Added T_{IOL_IDELAY_RESOLUTION}.
MMCM Switching Characteristics	Extensive updates to table and notes including removal of T_{DESKEWMISMATCH_MMCM}.
DPLL Switching Characteristics	Extensive updates to table and notes including removal of T_{DESKEWMISMATCH_DPLL}.
XPLL Switching Characteristics	Extensive updates to table and notes including removal of T_{DESKEWMISMATCH_XPLL}.
Device Pin-to-Pin Output Parameter Guidelines	Updated the XCVM1802 parameters in Vivado Design Suite 2020.3 v2.00.
Device Pin-to-Pin Input Parameter Guidelines	Updated the XCVM1802 parameters in Vivado Design Suite 2020.3 v2.00.
Package Parameter Guidelines	Updated the XCVM1802 package skew in Vivado Design Suite 2020.3 v2.00.
Memory Interface Controller	Added Notes 2 and 3. Updated 6.
GTY and GTYP Transceiver DC Input and Output Levels	Revised V_IN in Table 1. Updated the specifications in Table 3.
GTY and GTYP Transceiver Performance	Updated the F_GTYLRANGE values.
GTY and GTYP Transceiver PLL/Lock Time Adaptation	Added conditions to T_LOCK.
GTY and GTYP Transceiver Transmitter and Receiver Switching Characteristics	Removed legacy content and updated the applicable symbols, conditions, and values in both the Transmitter and Receiver tables.
GTY and GTYP Transceiver Electrical Compliance	Added the table.
PMC Quad-SPI Controller Interface	Added additional load information to the table.
Integrated Block for MRMAC	Changed title and added specifications.
Programmable Logic Integrated Block for PCIe	Added Table 1.
7/16/2020 Version 1.0
Initial release.	N/A