Device Pin-to-Pin Input Parameter Guidelines

Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
Document ID
DS957
Release Date
2024-02-29
Revision
1.8 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With MMCM (Internal Mode)
Symbol Description Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-2 -2 -1 -1MM -2LLI -2LSE

-2LLE

 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TSUMMCM_VC1502 Global clock input and input flip-flop (or latch) with MMCM Setup XCVC1502 –0.85 –0.87 –0.87 N/A –0.82 –0.84 –0.84 ns
THMMCM_VC1502 Hold 3.79 4.43 4.56 N/A 4.17 4.47 4.63 ns
TSUMMCM_VC1702 Setup XCVC1702 –0.67 –0.68 –0.68 N/A –0.62 –0.64 –0.64 ns
THMMCM_VC1702 Hold 3.79 4.43 4.56 N/A 4.17 4.47 4.63 ns
TSUMMCM_XQ_VC1702 Setup XQVC1702 N/A –0.68 –0.68 –0.64 N/A N/A –0.64 ns
THMMCM_XQ_VC1702 Hold N/A 4.43 4.56 4.59 N/A N/A 4.63 ns
TSUMMCM_VC1802 Setup XCVC1802 –0.90 –0.97 –0.97 N/A –0.91 –0.93 –0.93 ns
THMMCM_VC1802 Hold 4.16 4.80 4.98 N/A 4.81 4.80 5.00 ns
TSUMMCM_VC1902 Setup XCVC1902 –0.90 –0.97 –0.97 N/A –0.91 –0.93 –0.93 ns
THMMCM_VC1902 Hold 4.16 4.80 4.98 N/A 4.81 4.80 5.00 ns
TSUMMCM_XQ_VC1902 Setup XQVC1902 N/A –0.97 –0.97 –0.93 N/A N/A –0.93 ns
THMMCM_XQ_VC1902 Hold N/A 4.80 4.98 5.06 N/A N/A 5.00 ns
TSUMMCM_VC2602 Setup XCVC2602 –0.62 –0.66 –0.66 N/A   –0.62 –0.62 ns
THMMCM_VC2602 Hold 3.80 4.13 4.27 N/A   4.17 4.34 ns
TSUMMCM_VC2802 Setup XCVC2802 –0.62 –0.66 –0.66 N/A   –0.62 –0.62 ns
THMMCM_VC2802 Hold 3.80 4.13 4.27 N/A   4.17 4.34 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.