Device Pin-to-Pin Output Parameter Guidelines

Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)

Document ID

DS957

Release Date

2024-02-29

Revision

1.8 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol	Description^{1, 2}	Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)							Units
			0.88V (H)	0.80V (M)			0.70V (L)
			-2	-2	-1	-1MM	-2LLI	-2LSE -2LLE	-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
T_ICKOFMMCM	Global clock input and output flip-flop with MMCM	XCVC1502	6.97	7.52	7.98	N/A	8.21	8.21	8.81	ns
		XCVC1702	6.97	7.52	7.98	N/A	8.21	8.21	8.81	ns
		XQVC1702	N/A	7.52	7.98	8.04	N/A	N/A	8.81	ns
		XCVC1802	7.37	8.07	8.56	N/A	8.73	8.73	9.37	ns
		XCVC1902	7.37	8.07	8.56	N/A	8.73	8.73	9.37	ns
		XQVC1902	N/A	8.07	8.56	8.67	N/A	N/A	9.37	ns
		XCVC2602	6.73	7.31	7.78	N/A		8.00	8.61	ns
		XCVC2802	6.73	7.31	7.78	N/A		8.00	8.61	ns
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.