The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
2/29/2024 Version 1.8 | |
General updates | Updated Table 1, Speed Grade Designations, and Production Silicon and Software Status, to include the production release of the -2MSE, -2MLE, -2MSI, -2MLI, -2LSE,
-2LLE, -1MSE, -1MSI, -1MLI, -1LSE, -1LSI, -1LLI speed grades for XCVC2602 and
XCVC2802 using the Vivado Design Suite 2023.2.1
v2.00. This includes updates to the following tables: |
Absolute Maximum Ratings | Revised the transceiver REFCLK_AC maximum input voltage from 1.200V to 1.350V. |
Device Identification | Updated the device ID for XCVC2802. |
Block RAM Switching Characteristics | Changed maximum value of both TRCKO_DO and TRCKO_DO_REG in the -2LLI speed grade. |
DDR4 and LPDDR4/4X Memory Interface Controller | Removed the LPDDR4/4X pin efficient component interface limitation. |
Table 2 | Removed the rows, columns, and interface tiles connected to PL columns. See Versal Architecture and Product Data Sheet: Overview (DS950) for the most up to date information. |
Table 2 | Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV. |
GTY and GTYP Transceiver User Clock Switching Characteristics | Updated the -2H values. |
11/09/2023 Version 1.7 | |
General updates | Updated Table 1 and Production Silicon and Software Status including production release of the -2LLI speed grades for XCVC1502 and XCVC1702 using the Vivado Design Suite 2023.2 v2.04. |
Removed VC1352 device throughout data sheet. | |
For XCVC2602 and XCVC2802, removed -3H speed grade and added -2HSI/-2LLI speed grades throughout data sheet. | |
Absolute Maximum Ratings | Added Note 10. |
Recommended Operating Conditions | Updated Note 9 with PSIO operation information. Updated Note 10. |
Available Speed Grades and Operating Voltages | Updated Note 4. |
Device Pin-to-Pin Output Parameter Guidelines | Updated values in table to Vivado Design Suite 2023.2 speed files. |
Device Pin-to-Pin Input Parameter Guidelines | Updated values in table to Vivado Design Suite 2023.2 speed files. |
DDR4 and LPDDR4/4X Memory Interface Controller | Clarified the values for LPDDR4/4X XPIO bank performance. |
GTY and GTYP Transceiver Reference Clock Switching Characteristics | Added Note 1. |
GTY and GTYP Transceiver Digital Monitor Clock | Added table. |
GTY and GTYP Transceiver Electrical Compliance | Added the PCI Express 5.0 protocol for GTYP transceivers. |
5/09/2023 Version 1.6 | |
Summary | Clarified that the I and M temperature grades are also supported by the Versal AI Core devices. |
Absolute Maximum Ratings | Removed unused VCC_VDU. |
Recommended Operating Conditions | Updated Tj to add military (M) temperature specifications. |
DC Characteristics Over Recommended Operating Conditions | Added IL specifications. |
VIN Maximum Allowed AC Voltage Overshoot and Undershoot | Added Note 3 and Note 4 for -1MSM devices. |
Production Silicon and Software Status | Added the XCVC1502 and XCVC1702 in the -2HSI speed grade using the Vivado tools 2022.2.2 v2.02. |
Table 4 | Added Notes 1, 2, and 3. |
Table 5 | Added Notes 2, 4, 6, 8, 10, and 12. |
PS Gigabit Ethernet MAC Controller Interface | Added Note 2 to FGEMTSUREFCLK. |
Package Parameter Guidelines | Corrected the XCVC2602 and XCVC2902 package to VSVH1760. |
GTY and GTYP Transceiver DC Input and Output Levels | Removed the row for VCMOUTDC when remote RX is terminated to GND and added Note 2. Updated Note 3. |
3/28/2023 Version 1.5 | |
General updates | Updated the Table 1 including:
|
Added Note 4 to Production Silicon and Software Status. | |
Moved XQRVC1902 devices to a separate data sheet. | |
Recommended Operating Conditions | Updated VCCINT with values for -2LLI devices and added Note 7. |
Available Speed Grades and Operating Voltages | Updated -2LLI device code and added Note 5. |
Updated VCC_CPM5 values because devices with CPM5 do not support the -2HSI or -2LLI speed grades. | |
Updated Notes 1, 2, and 3. | |
DC Characteristics Over Recommended Operating Conditions | Updated the ICC_BATT conditions and values. |
Power Supply Requirements | Updated description to add references to the PDM tool. |
Speed Grade Designations | Removed -2MLI, -2LLI, -1MLI, and -1LLI speed grades from the XQVC1352 and XQVC1702. Moved some device/speed grade combinations to engineering sample. |
Production Silicon and Software Status | Added N/A to the columns for XQ devices that do not support low static-power grades. |
Production Silicon and Software Status | Added Note 4 to Production Silicon and Software Status. |
Device Identification | Updated the XCVC1502 and XCVC1702 IDCODEs. |
Processing System Performance Characteristics | Updated notes in Table 1 and Table 2. |
PMC JTAG and SelectMAP | Added Note 1 to FTCK. |
PMC Quad-SPI Controller Interface | Updated the FQSPI_REFCLK maximum for Quad-SPI device clock frequency operating at ≤37.5 MHz (Loopback disabled) from 150 MHz to 300 MHz. |
PMC SD/SDIO Controller Interface | Added TSDDCK and TSDCKD to the table and revised the minimum value for TSDSDR12DCK to 10.0 ns. |
PMC eMMC Controller Interface | Added TEMMCDCK and TEMMCCKD. |
Block RAM Switching Characteristics | Added -2LLI column. |
Accelerator RAM Switching Characteristics | Revised the -3 and -2 (VCC_PSLP = 0.88V) maximum accelerator RAM clock frequency. |
Device Pin-to-Pin Output Parameter Guidelines | Revised values for VC1502 and VC1702. Added -1MM and -2LLI columns. |
Device Pin-to-Pin Input Parameter Guidelines | Revised values for VC1502 and VC1702. Added -1MM and -2LLI columns. |
AI Engine Switching Characteristics | Revised values for VC1502 and VC1702. |
Table 1 | Revised VCMOUTDC and VCMOUTAC equations. |
Table 3 | Updated VOL, VOH, and VCMOUT minimum/maximum values. |
GTY and GTYP Transceiver Performance | In Table 1, revised the GTYP maximum line rate and the LCPLL line rate range. |
GTY and GTYP Transceiver User Clock Switching Characteristics | Updated FTXIN and FRXIN values for some data width conditions. |
Table 4 | Revised some of the -1 (VCCINT_CPM5 = 0.70V) overdrive values. |
Table 5 | Revised some of the overdrive mode frequencies. |
Table 6 | Revised some of the -1 (VCCINT = 0.70V) overdrive values. |
Video Decoder Engines Performance | Updated values and added Note 1. |
5/03/2022 Version 1.4 | |
General updates | Added XQ devices: XQVC1352, XQVC1702, XQVC1902, and XQRVC1902. |
Absolute Maximum Ratings | Updated the GT Transceivers VIN specification by adding unpowered and powered values for VIN_DC and VIN_AC. Removed duplicate IDCIN-FLOAT rating and note. Removed note 9. |
Available Speed Grades and Operating Voltages | Added the -1MSM speed grade for XQ devices (-1MM-m-S device code). |
Power Supply Requirements | Updated description. |
AC Switching Characteristics | Updated the Table 1 including production release of some of the devices/speed grade/operating voltages using the Vivado Design Suite 2022.1 v2.06 in Speed Grade Designations and Production Silicon and Software Status. |
Clocks and Reset | Added note 2 to Table 1. |
PMC Octal-SPI Controller Interface | Added values to Table 1 and updated note 1. |
PMC SD/SDIO Controller Interface | Added values to Table 1 and updated note 1. |
PMC eMMC Controller Interface | Added values and notes 3 and 4 to Table 1 and updated note 1. |
DDR4 and LPDDR4/4X Memory Interface Controller | Added note 7 to Table 1 |
GTY and GTYP Transceiver Performance | Added the -2H column. Some XC devices offer a -2HSI device and others offer a -3SE device. See the Speed and Temperature Grade table in the Versal Architecture and Product Data Sheet: Overview (DS950). |
Programmable Logic Integrated Block for PCIe | Updated Table 1. |
1/06/2022 Version 1.3 | |
Summary and General Updates | Added the XCVC2602 and XCVC2802 devices. |
Added the PCIe 5.0 and CPM5 specifications where applicable. They are available in the XCVC2602 and XCVC2802 devices. | |
Absolute Maximum Ratings | Revised the maximum VCCO from 3.465V to 3.63V for certain HDIO and PSIO banks. |
Added VREF specifications. | |
Removed TSOL guidelines. See Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for appropriate specifications by package type. | |
DC Characteristics Over Recommended Operating Conditions | Updated the HDIO, PSIO, and XPIO maximum capacitance and added Note 2. |
Available Speed Grades and Operating Voltages | Added the Vivado Design Tools Device Code column. |
AC Switching Characteristics | Updated to Vivado Design Suite 2021.2.1 v2.05 for the XCVC1802 and XCVC1902. |
Added the Evaluation Product Specification description. | |
Speed Grade Designations | Revised the available speed specifications by device. |
Production Silicon and Software Status | Revised the production released version of the XCVC1802 and XCVC1902 to Vivado Design Suite 2021.2.1 v2.05 and added Note 3 |
PS USB Controller Interface | Revised TULPICKD input hold time from 0 to 0.5 ns (500 ps). |
Table 4 | Added Note 4 limiting the RLDRAM3 maximum performance for -2L and -1L speed grades. |
Device Pin-to-Pin Output Parameter Guidelines | Revised the XCVC1802 and XCVC1902 speed specification values for Vivado Design Suite 2021.2.1 v2.05. |
Device Pin-to-Pin Input Parameter Guidelines | Revised the XCVC1802 and XCVC1902 speed specification values for Vivado Design Suite 2021.2.1 v2.05. |
GTY and GTYP Transceiver Configuration Interface Port Switching Characteristics | Reduced the maximum GTYAPB3CLK frequency in Table 1. |
GTY and GTYP Transceiver User Clock Switching Characteristics | Updated values in Table 2. |
7/01/2021 Version 1.2 | |
Recommended Operating Conditions | Added Note 10. |
AC Switching Characteristics | Updated the speed file versions to Vivado Design Suite 2021.1 v2.01. |
Speed Grade Designations | Moved the XCVC1802 and XCVC1902 to production for the
following speed grades:
|
Production Silicon and Software Status | Updated the software status for the following speed grades to
Vivado Design Suite 2021.1 v2.01.
|
Processing System Performance Characteristics | In Table 1, updated FRPUMAX for the -3/-2 (0.88V (H)) speed grades. |
Added FPLATB_CLK to Table 2. | |
PS CAN FD Controller Interface | Added Note 2. |
PS Trace Interface | Updated Note 2 and added Note 4. |
Programmable Logic Performance Characteristics | Updated Table 3 for -2/-1 (0.80V (M) and 0.70V (L)) speed grades. |
In Table 4:
|
|
Device Pin-to-Pin Output Parameter Guidelines | Updated the TICKOFMMCM values to the speed specifications in Vivado Design Suite 2022.2.2. Added -1MM and -2LLI columns. |
Device Pin-to-Pin Input Parameter Guidelines | Updated the setup and hold values to the speed specifications in Vivado Design Suite 2022.2.2. Added -1MM and -2LLI column. |
DDR4 and LPDDR4/4X Memory Interface Controller | Added Note 1 to Table 1, and updated Note 5. |
GTY and GTYP Transceiver User Clock Switching Characteristics | Updated values in Table 2. |
4/14/2021 Version 1.1 | |
General | Added GTYP transceiver specifications. |
Summary | Added VCC_PMC overdrive support. |
Table 1 | Updated the notes. |
Table 1 | Revised maximum VCCBATT, added minimum CFU reference clock frequency to FCFU_REFCLK, added overdrive conditions to VCC_PMC , added Notes 2, 3, 4, 9, 13, and updated Note 16. |
Available Speed Grades and Operating Voltages | Updated table with standard and overdrive modes. Added note 4. |
Table 1 | Added table. |
VIN Maximum Allowed AC Voltage Overshoot and Undershoot | Added note 3 to Table 2. |
Table 3 | Updated VIL maximum and VIH minimum for LVSTL06_12 and LVSTL_11. |
Table 8 | Removed LVSTL_11 (VOH = 33). Added Note 2. |
Table 9 | Removed LVSTL_11 (VOH = 33). |
LVDS DC Specifications (LVDS15) | Added VICM_AC and Note 5. |
AC Switching Characteristics | Updated the speed file versions and the definitions for engineering sample, pre-production, and production product specification. |
Speed Grade Designations | Moved the XCVC1802 and XCVC1902 to production for the
following speed grades:
|
Production Silicon and Software Status | The XCVC1802 and XCVC1902 is production released using Vivado Design Suite 2020.3 v2.00. |
Device Identification | Updated the IDCODE for the XCVC1802 and XCVC1902, and added notes to explain the table fields. |
Processing System Performance Characteristics | Updated Table 1. |
Updated descriptions, added FPSFCIDMA_CLK and Note 3 to Table 2. | |
Clocks and Reset | Added TMODEPOR, and TPORMODE to Table 3. |
Added FFPD_LSBUS_CLK and Note 4 to Table 4. | |
Added FRPLL_TO_XPD_CLK, FLPD_LSBUS_CLK, FTS_REFCLK, FPSM_REFCLK, FDBG_LPD_CLK, FUSB_REFCLK, FDBG_TS_CLK, and Notes 1, 5, 7, and 11 to Table 5. | |
In Table 6, updated the IRO tolerance range. | |
In Table 7, added FEFUSE_REFCLK, FSMON_REFCLK, FNPI_REFCLK, FPPLL_TO_XPD_CLK, FNPLL_TO_XPD_CLK, FLSBUS_REFCLK, FAXI_TO_REFCLK, FUSB_SREFCLK, and FHSM0_REFCLK. Revised the -3 specifications for FPL0_REFCLK, FPL1_REFCLK, FPL2_REFCLK, and FPL3_REFCLK. Updated the Notes 1 and 5. | |
Added Note 1 to Table 8. | |
PMC JTAG and SelectMAP | Extensive updates to Table 1 and Table 2. |
PMC Quad-SPI Controller Interface | Extensive changes to the table. Updated Note 1 and added Note 2 and 5. |
PMC Octal-SPI Controller Interface | Removed load condition column. Updated Note 1. |
PS USB Controller Interface | Added TULPIDCK, TULPICKD, and TULPICKO. |
PS Gigabit Ethernet MAC Controller Interface | Added FGEMTSUREFCLK. |
PS General Purpose I/O Interface | Removed load condition column. |
PS Trace Interface | Updated FTCECLK and Note 3. |
PS Triple-timer Counter Interface | Extensive additions and edits to both the table and notes. |
Network on Chip Switching Characteristics | Updated the performance values in the table. |
Programmable Logic Performance Characteristics | Updated values in Table 1. Updated values in Table 2 and added Notes 3 and 4. Updated the values in Table 3. Updated the values in Table 4 and added Note 4: Maximum performance for interfaces using more than one bank. Removed the LVDS Native-Mode 1000BASE-X Support table. |
Block RAM Switching Characteristics | Updated TRCKO_DO and TRCKO_DO_REG. |
Input/Output Delay Switching Characteristics | Added TIOL_IDELAY_RESOLUTION. |
MMCM Switching Characteristics | Extensive updates to table and notes including removal of TDESKEWMISMATCH_MMCM. |
DPLL Switching Characteristics | Extensive updates to table and notes including removal of TDESKEWMISMATCH_DPLL. |
XPLL Switching Characteristics | Extensive updates to table and notes including removal of TDESKEWMISMATCH_XPLL. |
Device Pin-to-Pin Output Parameter Guidelines | Updated the XCVC1802 and XCVC1902 parameters in Vivado Design Suite 2020.3 v2.00. |
Device Pin-to-Pin Input Parameter Guidelines | Updated the XCVC1802 and XCVC1902 parameters in Vivado Design Suite 2020.3 v2.00. |
Package Parameter Guidelines | Updated the XCVC1802 and XCVC1902 package skew in Vivado Design Suite 2020.3 v2.00. |
DDR4 and LPDDR4/4X Memory Interface Controller | Added Notes 2 and 3. Updated Note 6. |
GTY and GTYP Transceiver DC Input and Output Levels | Revised VIN in Table 1. Updated the specifications in Table 3. |
GTY and GTYP Transceiver Performance | Updated the FGTYLRANGE values. |
GTY and GTYP Transceiver PLL/Lock Time Adaptation | Added conditions to TLOCK. |
GTY and GTYP Transceiver Transmitter and Receiver Switching Characteristics | Removed legacy content and updated the applicable symbols, conditions, and values in both the Transmitter and Receiver tables. |
GTY and GTYP Transceiver Electrical Compliance | Added the table. |
PMC Quad-SPI Controller Interface | Added additional load information to the table. |
Integrated Block for MRMAC | Changed title and added specifications. |
Programmable Logic Integrated Block for PCIe | Added Table 1. |
7/16/2020 Version 1.0 | |
Initial release. | N/A |