Device Pin-to-Pin Input Parameter Guidelines

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-02-29
Revision
1.6 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With MMCM (Internal Mode)
Symbol Description Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-2 -2 -1 -2LLI -2LSE

-2LLE

 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TSUMMCM_VE1752 Global clock input and input flip-flop (or latch) with MMCM Setup XCVE1752 –0.67 –0.68 –0.68 –0.62 –0.64 –0.64 ns
THMMCM_VE1752 Hold 3.79 4.43 4.56 4.17 4.47 4.63 ns
TSUMMCM_VE2002 Setup XCVE2002 –0.68 –0.67 –0.67   –0.68 –0.68 ns
THMMCM_VE2002 Hold 2.91 3.22 3.34   3.22 3.36 ns
TSUMMCM_VE2102 Setup XCVE2102 –0.68 –0.67 –0.67   –0.68 –0.68 ns
THMMCM_VE2102 Hold 2.91 3.22 3.34   3.22 3.36 ns
TSUMMCM_VE2202 Setup XCVE2202 –0.49 –0.51 –0.51   –0.48 –0.48 ns
THMMCM_VE2202 Hold 2.78 3.01 3.12   3.05 3.19 ns
TSUMMCM_VE2302 Setup XCVE2302 –0.49 –0.51 –0.51   –0.48 –0.48 ns
THMMCM_VE2302 Hold 2.78 3.01 3.12   3.05 3.19 ns
TSUMMCM_VE2602 Setup XCVE2602 –0.62 –0.66 –0.66   –0.62 –0.62 ns
THMMCM_VE2602 Hold 3.80 4.13 4.27   4.17 4.34 ns
TSUMMCM_VE2802 Setup XCVE2802 –0.62 –0.66 –0.66   –0.62 –0.62 ns
THMMCM_VE2802 Hold 3.80 4.13 4.27   4.17 4.34 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.