More information and documentation on solutions for
PCI Express®
designs can be found at
PCI Express
. The
Versal
Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each
Versal device.
Table 1. Maximum Performance for Programmable Logic Integrated Block for
PCIe Rev. 4.0
Symbol |
Description
1
|
Performance as a Function of
Speed Grade and Operating Voltage (VCCINT) |
Units |
0.88V (H) |
0.80V (M) |
0.70V (L) |
-2 |
-2 |
-1 |
-2 |
-1 |
FPIPECLK
|
Pipe clock maximum frequency |
500 |
500 |
500 |
500 |
500 |
MHz |
FCORECLK
|
Core clock maximum frequency |
500 |
500 |
500 |
500 |
500 |
MHz |
FAPBCLK
|
APB clock maximum frequency |
250 |
250 |
250 |
250 |
250 |
MHz |
-
PCI Express Gen4 operation is supported for x1, x2, x4, and x8
widths.
|
Table 2. Maximum Performance for Programmable Logic Integrated Block for
PCIe Rev. 5.0
Symbol |
Description
1
|
Performance as a Function of
Speed Grade and Operating Voltage (VCCINT) |
Units |
0.88V (H) |
0.80V (M) |
0.70V (L) |
-2 |
-2 |
-1 |
-2 |
-1 |
FPIPECLK
|
Pipe clock maximum frequency |
500 |
500 |
500 |
500 |
500 |
MHz |
FCORECLK
|
Core clock maximum frequency |
500 |
500 |
500 |
500 |
500 |
MHz |
FAPBCLK
|
APB clock maximum frequency |
250 |
250 |
250 |
250 |
250 |
MHz |
-
PCI Express Gen4 operation is supported for x1, x2, x4, and x8
widths.
|