Clock Buffers and Networks

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English
Table 1. Clock Buffers Switching Characteristics (including Multi-clock Buffers)
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
Global Clock Switching Characteristics (Including BUFGCTRL and MBUFGCTRL)
FMAX Maximum frequency of a global clock tree (BUFG) 1150 1150 1070 984 800 680 MHz
Global Clock Buffer with Input Divide Capability (BUFGCE_DIV and MBUFGCE_DIV)
FMAX Maximum frequency of a global clock buffer with input divide capability 1150   1070 984 800 680 MHz
Global Clock Buffer with Clock Enable (BUFGCE)
FMAX Maximum frequency of a global clock buffer with clock enable 1150 1150 1070 984 800 680 MHz
Global Clock Buffer with for the Processing System (BUFG_PS and MBUFG_PS)
FMAX Maximum frequency of a global clock buffer with clock enable 1150 1150 1070 984 800 680 MHz
GTYP or GTM Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT and MBUFG_GT)
FMAX Maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 1150 1150 1070 984 1000 680 MHz