Clocks and Reset

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English
Table 1. Reference Clock Requirements
Symbol Description Min Max Units
FREFCLK Reference clock (REF_CLK) frequency 27 60 MHz
TRMSJ_REFCLK REF_CLK input RMS clock jitter 3 ps
TINPJ_REFCLK

REF_CLK input period jitter (peak-to-peak)

Number of clock cycles = 10,000

50 ps
TDC_REFCLK REF_CLK duty cycle 45 55 %
TREFCLK REF_CLK rise time (20%–80%) and fall time (80%–20%) at 3.3V 3 ns
REF_CLK rise time (20%–80%) and fall time (80%–20%) at 1.8V or 2.5V 3.5 ns
REF_CLK rise time (10%–90%) and fall time (90%–10%) at 3.3V 4 ns
REF_CLK rise time (10%–90%) and fall time (90%–10%) at 1.8V or 2.5V 4.66 ns
  1. The FREFCLK clock frequency range and TDC_REFCLK duty cycle specifications also apply to the PL alternative reference clock inputs (PL_PMC_ALT_REF_CLK, PL_LPD_ALT_REF_CLK, and PL_FPD_ALT_REF_CLK).
  2. See Table 3 for REF_CLK operating requirements with respect to the POR_B input.
  3. Some devices have one REF_CLK input pin, and some devices have two input pins: REF_CLK0 and REF_CLK1. For devices with two REF_CLK input pins, REF_CLK0 and REF_CLK1 must be supplied from the same clock source. See REF_CLK recommendations in the Versal ACAP PCB Design User Guide (UG863).
Table 2. RTC Crystal Requirements
Symbol Description Min Typ Max Units
FXTAL Parallel resonance crystal frequency 32.768 kHz
TFTXTAL Frequency tolerance –20 20 ppm
CXTAL Load capacitance for crystal parallel resonance 12.5 pF
RESR Crystal ESR (16.8 and 19.2 MHz) 70
CSHUNT Crystal shunt capacitance 1.4 pF
Table 3. Power-on Reset Assertion Timing Requirements
Symbol Description Min Typ Max Units
TPOR_B Required POR_B assertion time 1, 2 10 µs
TMODEPOR MODE[3:0] setup time to POR_B rising edge 74 ns
TPORMODE POR_B rising edge to MODE[3:0] hold time 74 ns
  1. The POR_B input must be asserted Low during the power-on sequence and continue to be asserted for a duration TPOR_B after all the required supplies of the PMC have reached minimum voltage levels. The PS, system, and PL domains can be independently powered on or off with additional power management. If the PS, system, and/or PL domains are expected to be functional at initial power-on without additional power management, then the POR_B input must be held Low until all required domain power supplies have also reached minimum voltage levels. For additional power-on sequence information, refer to the Xilinx Power Estimator (XPE). For additional power management information, see the Versal ACAP Technical Reference Manual (AM011) or the Versal ACAP System Software Developers Guide (UG1304).
  2. Before the deassertion of POR_B, the REF_CLK must be operating within specification.
Table 4. PS FPD Clocks Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PSFP) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FFPD_LSBUS_CLK Maximum FPD LSBUS clock frequency 150 150 150 150 100 100 1 MHz
FFPD_TOPSW_CLK Maximum FPD top-switch clock frequency 1000 950 825 800 600 550 2 MHz
FDBG_FPD_CLK Maximum debug FPD clock frequency 400 400 400 400 400 333 3 MHz
  1. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum FPD LSBUS clock frequency is 150 MHz when VCC_PSFP = 0.88V.
  2. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum FPD top-switch clock frequency is 800 MHz when VCC_PSFP = 0.88V.
  3. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum debug FPD clock frequency is 400 MHz when VCC_PSFP = 0.88V.
Table 5. PS LPD Clocks Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PSLP) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FRPLL_TO_XPD_CLK Maximum RPU PLL to XPD clock frequency 1200 1200 1200 1200 1000 1000 MHz
FLPD_TOPSW_CLK Maximum LPD top-switch clock frequency 1 750 700 600 600 450 400 2 MHz
FLPD_LSBUS_CLK Maximum LPD LSBUS clock frequency 1 150 150 150 150 100 100 3 MHz
FIOP_SW_CLK Maximum I/O peripherals (IOP) switch clock frequency 250 250 250 250 250 250 MHz
FTS_REFCLK Maximum time-stamp reference clock frequency 100 100 100 100 100 100 MHz
FPSM_REFCLK Maximum PS manager (PSM) reference clock frequency 460 460 460 460 368 368 4 MHz
FDBG_LPD_CLK Maximum debug LPD clock frequency 400 400 400 400 400 333 5 MHz
FDBG_TS_CLK Maximum debug time-stamp clock frequency 400 400 400 400 400 333 6 MHz
FUSB_REFCLK Maximum USB reference clock frequency 60 60 60 60 60 60 MHz
FCPM4_TOPSW_CLK Maximum CPM4 top-switch clock frequency 1000 950 825 800 600 550 MHz
  1. The LPD_TOPSW_CLK operating frequency must be greater than the LPD_LSBUS_CLK operating frequency.
  2. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum LPD top-switch clock frequency is 600 MHz when VCC_PSLP = 0.88V.
  3. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum LPD LSBUS clock frequency is 150 MHz when VCC_PSLP = 0.88V.
  4. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum PSM reference clock frequency is 400 MHz when VCC_PSLP = 0.88V.
  5. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum debug LPD clock frequency is 400 MHz when VCC_PSLP = 0.88V.
  6. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum debug time-stamp clock frequency is 400 MHz when VCC_PSLP = 0.88V.
Table 6. PMC IRO Clock Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FPMC_IRO_CLK PMC internal clock source typical frequency 400 400 400 400 320 320 MHz
PMC internal clock source tolerance +10/–17 +10/–17 +10/–17 +10/–17 +10/–17 +10/–17 %
Table 7. PMC Clocks Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FEFUSE_REFCLK Maximum eFUSE reference clock frequency for reading 115 115 115 115 92 92 MHz
Maximum eFUSE reference clock frequency for programming 60 60 60 60 60 60 MHz
FSMON_REFCLK Maximum system monitor reference clock frequency 300 300 300 300 300 300 MHz
FUSB_SREFCLK Maximum USB suspend reference clock frequency 115 115 115 115 92 92 MHz
FAXI_TO_REFCLK Maximum AXI4 timeout reference clock frequency 115 115 115 115 92 92 MHz
FCFU_REFCLK Maximum configuration frame unit (CFU) reference clock frequency 1 400 400 400 400 320 320 MHz
Minimum CFU reference clock frequency 20 20 20 20 20 20 MHz
FLSBUS_REFCLK Maximum PMC LSBUS reference clock frequency 150 150 150 150 100 100 MHz
FNPI_REFCLK Maximum NoC programming interface (NPI) reference clock frequency 300 300 300 300 300 300 MHz
FHSM1_REFCLK Maximum horizontal super module (HSM1) reference clock frequency used with XPIO 2 200 200 200 200 200 200 MHz
FPL0_REFCLK Maximum PL0 reference clock frequency 400 400 350 350 300 250 3 MHz
FPL1_REFCLK Maximum PL1 reference clock frequency 400 400 350 350 300 250 3 MHz
FPL2_REFCLK Maximum PL2 reference clock frequency 400 400 350 350 300 250 3 MHz
FPL3_REFCLK Maximum PL3 reference clock frequency 400 400 350 350 300 250 3 MHz
FPPLL_TO_XPD_CLK Maximum PMC PLL to XPD clock frequency 1200 1200 1200 1200 1000 1000 MHz
FNPLL_TO_XPD_CLK Maximum NoC PLL to XPD clock frequency 1200 1200 1200 1200 1000 1000 MHz
  1. The maximum configuration frame interface (CFI) clock frequency is the same as the CFU reference clock. When the programmable device image (PDI) is compressed, the compressed data rate through the CFU decompressor is limited to half of the CFI data rate.
  2. When the HSM1 reference clock is used as the source clock to the XPLL, the frequency range is limited from 100 MHz to 200 MHz.
  3. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum PL0, PL1, PL2, and PL3 reference clock frequency is 280 MHz when VCC_PMC = 0.88V.
Table 8. PMC PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FPMCPLL PMC PLL output frequency 2000 2000 1800 1600 1300 1300 1 MHz, Max
270 270 270 270 270 270 MHz, Min
FPMCPLLVCO PMC PLL VCO frequency 4320 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 2160 MHz, Min
TPMCPLLLOCK PMC PLL lock time 100 100 100 100 100 100 μs, Max
  1. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum reference clock frequency is 1600 MHz when VCC_PMC = 0.88V.
Table 9. NoC PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PMC) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FNOCPLL NoC PLL output frequency 2000 2000 1800 1600 1300 1300 MHz, Max
270 270 270 270 270 270 MHz, Min
FNOCPLLVCO NoC PLL VCO frequency 4320 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 2160 MHz, Min
TNOCPLLLOCK NoC PLL lock time 100 100 100 100 100 100 μs, Max
Table 10. PS APU PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PSFP) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FPSAPLL APU PLL output frequency 2000 2000 1800 1600 1300 1300 1 MHz, Max
270 270 270 270 270 270 MHz, Min
FPSAPLLVCO APU PLL VCO frequency 4320 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 2160 MHz, Min
TPSAPLLLOCK APU PLL lock time 100 100 100 100 100 100 μs, Max
  1. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum reference clock frequency is 1600 MHz when VCC_PSFP = 0.88V.
Table 11. PS RPU PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_PSLP) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FPSRPLL RPU PLL output frequency 2000 2000 1800 1600 1300 1300 1 MHz, Max
270 270 270 270 270 270 MHz, Min
FPSRPLLVCO RPU PLL VCO frequency 4320 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 2160 MHz, Min
TPSRPLLLOCK RPU PLL lock time 100 100 100 100 100 100 μs, Max
  1. The -1LLI and -1LSI low-power devices support an overdrive voltage where the maximum reference clock frequency is 1600 MHz when VCC_PSLP = 0.88V.
Table 12. CPM4 PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FCPM4PLL CPM4 PLL output frequency 1200 1080 900 900 810 720 MHz, Max
270 270 270 270 270 270 MHz, Min
FCPM4PLLVCO CPM4 PLL VCO frequency 4320 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 2160 MHz, Min
TCPM4PLLLOCK CPM4 PLL lock time 100 100 100 100 100 100 μs, Max
Table 13. CPM5 PLL Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_CPM5) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
FCPM5PLL CPM5 PLL output frequency 1200 900 900 725 725 MHz, Max
270 270 270 270 270 MHz, Min
FCPM5PLLVCO CPM5 PLL VCO frequency 4320 4320 4320 4320 4320 MHz, Max
2160 2160 2160 2160 2160 MHz, Min
TCPM5PLLLOCK CPM5 PLL lock time 100 100 100 100 100 μs, Max