Device Pin-to-Pin Input Parameter Guidelines

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID

DS959

Release Date

2022-05-02

Revision

1.0 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With MMCM (Internal Mode)
Symbol	Description		Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)						Units
				0.88V (H)		0.80V (M)		0.70V (L)
				-3	-2	-2	-1	-2	-1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.^{1, 2, 3}
T_{SUMMCM_VP1002}	Global clock input and input flip-flop (or latch) with MMCM	Setup	XCVP1002	N/A						ns
T_{HMMCM_VP1002}		Hold	XCVP1002	N/A						ns
T_{SUMMCM_VP1052}		Setup	XCVP1052	N/A						ns
T_{HMMCM_VP1052}		Hold	XCVP1052	N/A						ns
T_{SUMMCM_VP1102}		Setup	XCVP1102		N/A					ns
T_{HMMCM_VP1102}		Hold	XCVP1102		N/A					ns
T_{SUMMCM_VP1202}		Setup	XCVP1202	–1.28	N/A	–1.26	–1.26	–1.30	–1.30	ns
T_{HMMCM_VP1202}		Hold	XCVP1202	4.62	N/A	5.04	5.21	5.13	5.32	ns
T_{SUMMCM_VP1402}		Setup	XCVP1402							ns
T_{HMMCM_VP1402}		Hold	XCVP1402							ns
T_{SUMMCM_VP1502}		Setup	XCVP1502	–1.27	N/A	–1.25	–1.25	–1.29	–1.29	ns
T_{HMMCM_VP1502}		Hold	XCVP1502	4.63	N/A	5.06	5.23	5.14	5.33	ns
T_{SUMMCM_VP1552}		Setup	XCVP1552							ns
T_{HMMCM_VP1552}		Hold	XCVP1552							ns
T_{SUMMCM_VP1702}		Setup	XCVP1702	–1.26	N/A	–1.25	–1.25	–1.28	–1.28	ns
T_{HMMCM_VP1702}		Hold	XCVP1702	4.64	N/A	5.06	5.23	5.14	5.33	ns
T_{SUMMCM_VP1802}		Setup	XCVP1802	–1.26	N/A	–1.25	–1.25	–1.28	–1.28	ns
T_{HMMCM_VP1802}		Hold	XCVP1802	4.64	N/A	5.06	5.23	5.15	5.33	ns
T_{SUMMCM_VP2502}		Setup	XCVP2502		N/A					ns
T_{HMMCM_VP2502}		Hold	XCVP2502		N/A					ns
T_{SUMMCM_VP2802}		Setup	XCVP2802		N/A					ns
T_{HMMCM_VP2802}		Hold	XCVP2802		N/A					ns
Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. Use IBIS to determine any duty-cycle distortion incurred using various standards.