Device Pin-to-Pin Output Parameter Guidelines

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2023-11-09
Revision
1.4 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol Description 1, 2 Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -1MM -2LLI -2LSE

-2LLE

-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
TICKOFMMCM Global clock input and output flip-flop with MMCM XCVP1002 N/A 5.44 6.01 6.24 N/A 5.82 6.01 6.27 ns
XCVP1052 N/A 5.44 6.01 6.24 N/A 5.82 6.01 6.27 ns
XCVP1102 5.69 N/A 6.26 6.56 N/A N/A 6.33 6.64 ns
XCVP1202 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XQVP1202 N/A N/A 6.52 6.87 6.95 N/A N/A 6.89 ns
XCVP1402 7.18 N/A 7.78 8.25 N/A N/A 8.47 9.08 ns
XQVP1402 N/A N/A 7.78 8.25 8.32 N/A N/A 9.08 ns
XCVP1502 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XQVP1502 N/A N/A 6.52 6.87 N/A N/A N/A 6.89 ns
XCVP1552 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XCVP1702 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XCVP1802 5.87 N/A 6.52 6.87 N/A N/A 6.52 6.89 ns
XCVP1902   N/A     N/A N/A     ns
XCVP2502 6.25 N/A 6.81 7.10 N/A N/A 6.89 7.20 ns
XCVP2802 6.25 N/A 6.82 7.10 N/A N/A 6.90 7.20 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  2. MMCM output jitter is already included in the timing calculation.