Device Pin-to-Pin Output Parameter Guidelines

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID

DS959

Release Date

2022-12-05

Revision

1.1 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol	Description^{1, 2}	Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)						Units
			0.88V (H)		0.80V (M)		0.70V (L)
			-3	-2	-2	-1	-2	-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
T_ICKOFMMCM	Global clock input and output flip-flop with MMCM	XCVP1002	N/A						ns
		XCVP1052	N/A						ns
		XCVP1102		N/A					ns
		XCVP1202	6.08	N/A	6.57	6.93	6.75	7.12	ns
		XCVP1402		N/A					ns
		XCVP1502	6.25	N/A	6.82	7.10	6.90	7.20	ns
		XCVP1552	6.25	N/A	6.82	7.10	6.90	7.20	ns
		XCVP1702	6.25	N/A	6.82	7.10	6.90	7.21	ns
		XCVP1802	6.25	N/A	6.82	7.11	6.90	7.21	ns
		XCVP2502		N/A					ns
		XCVP2802		N/A					ns
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.