GTY and GTYP Transceiver PLL/Lock Time Adaptation

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English
Table 1. GTY and GTYP Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock Reference clock frequency ≥ 150 MHz 3 ms
Reference clock frequency < 150 MHz 5.7 ms
TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE) After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. 50,000 37 x 106 UI
Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled 50,000 2.3 x 106 UI