Input/Output Delay Switching Characteristics

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English
Table 1. Input/Output Delay Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
TIDELAY_RESOLUTION/ TODELAY_RESOLUTION XPHY IDELAY/ODELAY delay tap resolution 1.22 to 4.00 ps
TIDELAY_ERROR/ TODELAY_ERROR XPHY calibrated delay line error (DELAY_VALUE) (REFCLK_FREQUENCY = 500 to 1800 MHz) 1 –10 to +10 Delay Taps
TIOL_IDELAY_RESOLUTION/TIOL_ODELAY_RESOLUTION IOL IDELAY/ODELAY uncalibrated delay tap resolution for both HD and XP IOL resources 60 to 173 ps
  1. For REFCLK_FREQUENCY < 500 MHz, BISC calibration of the DELAY_VALUE_<0-5> is not guaranteed. Use the TIDELAY_RESOLUTION/TODELAY_RESOLUTION for delay calculations. Refer to the Versal ACAP SelectIO Resources Architecture Manual (AM010). IDELAY is used for alignment and ALIGN_DELAY effects the programmed DELAY_VALUE programming.