Integrated Block for MRMAC

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English
More information and documentation on solutions using the multirate Ethernet MAC (MRMAC) can be found at Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314). The Versal Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each Versal Premium device.
Table 1. Maximum Performance for MRMAC Designs
Symbol Description 1 Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -2 -1 -2 -1
FRX_CORE_CLK Receive core clock 725.000 705.250 705.250 664.063 705.250 644.531 MHz
FTX_CORE_CLK Transmit core clock 725.000 705.250 705.250 664.063 705.250 644.531 MHz
FRX_AXIS_CLK Receive AXI4-Stream interface clock 431.762 420.000 420.000 420.000 420.000 322.266 MHz
FTX_AXIS_CLK Transmit AXI4-Stream interface clock 431.762 420.000 420.000 420.000 420.000 322.266 MHz
FRX_SERDES_CLK Serializer/deserializer clock 725.000 664.063 664.063 664.063 664.063 644.531 MHz
FRX_ALT_SERDES_CLK 2 Receive alternate serializer/deserializer clock 362.500 352.625 352.625 332.031 352.625 322.266 MHz
FTX_ALT_SERDES_CLK 2 Transmit alternate serializer/deserializer clock 362.500 352.625 352.625 332.031 352.625 322.266 MHz
FRX_TS_CLK Receive timestamp clock 350.000 350.000 350.000 350.000 350.000 350.000 MHz
FTX_TS_CLK Transmit timestamp clock 350.000 350.000 350.000 350.000 350.000 350.000 MHz
FRX_FLEXIF_CLK Receive flex interface clock 431.762 420.000 420.000 420.000 420.000 322.266 MHz
FTX_FLEXIF_CLK Transmit flex interface clock 431.762 420.000 420.000 420.000 420.000 322.266 MHz
FAPB3_CLK AMBA® advance peripheral bus (APB3) clock 300.000 300.000 300.000 300.000 300.000 300.000 MHz
  1. Overclocking is only supported in 100 GbE (with FRX_CORE_CLK and FTX_CORE_CLK running at 706 MHz, and the FRX_SERDES_CLK running at 353 MHz) by faster speed grade devices (-3H, -2M, -2L).
  2. The ALT_SERDES_CLKs run at half the speed of the primary SERDES_CLK. See Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314) for more information.