Integrated High-speed Channelized Cryptography Engine

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English

This section describes the maximum performance for the integrated high-speed channelized cryptography (HSC) engine configurations.

Table 1. High-Speed Channelized Cryptography Engine Performance
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
FDEC_CORE_CLK Core clock for the decryption block 818.707 818.707 818.707 818.707 409.353 MHz
FENC_CORE_CLK Core clock for the encryption block 818.707 818.707 818.707 818.707 409.353 MHz
FDEC_EGR_AXIS_CLK Egress AXI-S clock for the decryption block 409.353 409.353 409.353 409.353 204.677 MHz
FENC_EGR_AXIS_CLK Egress AXI-S clock for the encryption block 409.353 409.353 409.353 409.353 204.677 MHz
FDEC_IGR_AXIS_CLK Ingress AXI-S clock for the decryption block 409.353 409.353 409.353 409.353 204.677 MHz
FENC_IGR_AXIS_CLK Ingress AXI-S clock for the encryption block 409.353 409.353 409.353 409.353 204.677 MHz
FAPB3_CLK APB3 clock 300.000 300.000 300.000 300.000 300.000 MHz