Memory Interface Controller

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-05-02
Revision
1.0 English

The following table provides the maximum data rates for applicable memory standards using the Versal Premium device memory PHY. Refer to Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the Versal ACAP PCB Design User Guide (UG863), electrical analysis, and characterization of the system.

Table 1. Maximum Physical Interface (PHY) Rate for Integrated Memory Interface Controller
Memory Standard DRAM Type DIMM Slots XPIO Bank Performance 1 Performance as a Function of Speed Grade and Operating Voltage (VCC_SOC) Units
0.88V (H) 0.80V (M) 0.80V (L) 2
-3 -2 -2 -1 -2 -1
DDR4 Single rank component 3 All 3200 3200 3200 3200 3200 3200 Mb/s
1 rank DIMM 4 , LRDIMM 5 1 All 3200 3200 3200 3200 3200 3200 Mb/s
2 rank DIMM 4 1 All 2933 2933 2933 2933 2933 2933 Mb/s
1 rank RDIMM,

2 rank LRDIMM

2 All 2667 2667 2667 2667 2667 2667 Mb/s
2 rank RDIMM 2 All 2133 2133 2133 2133 2133 2133 Mb/s
LPDDR4

LPDDR4X 7

Single rank component 6 High, Medium 4266 4266 3933 3733 3933 3733 Mb/s
Dual rank component High, Medium 3733 3733 3733 3733 3733 3733 Mb/s
Single rank component All 3200 3200 3200 3200 3200 3200 Mb/s
Dual rank component All 2933 2933 2933 2933 2933 2933 Mb/s
  1. The Versal ACAP package pinout files specify XPIO bank performance (XPIOperf). See the ASCII package files information in the Versal ACAP Packaging and Pinouts Architecture Manual (AM013).
  2. The integrated DDRMC is powered by the VCC_SOC supply that operates at 0.80V in low (L) voltage operation, see Table 1.
  3. For DDR4 DDP deep components, the maximum data rate is 2933 Mb/s for five or less DDP devices across all speed grades and temperature grades. For six or more DDP deep devices, the maximum data rate is 2133 Mb/s across all speed grades and temperature grades. For DDR4 DDP wide components, use single rank component data rates.
  4. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, and UDIMM.
  5. Includes 1 and 2 rank LRDIMM.
  6. The LPDDR4/4X pin efficient component interface is limited to 3733 Mb/s. See Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) for pin efficient component interfaces.
  7. For LPDDR4/4X, use the Vivado tool to determine the maximum performance by package and I/O bank combination.