PMC SD/SDIO Controller Interface

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
DS959
Release Date
2022-12-05
Revision
1.1 English
Table 1. SD/SDIO Interface
Symbol Description 1 Min Max Units
FSD_REFCLK SD reference clock frequency 200 MHz
FSDDLL_REFCLK SD DLL reference clock frequency 1200 MHz
SD/SDIO Interface Default Speed Mode
FSDS_CLK 2 SD standard device clock frequency 20 MHz
FSDID_CLK Clock frequency in identification mode 400 kHz
TSDDC_CLK SD standard device clock duty cycle 45 55 %
TSDCKO Clock to output delay, all outputs –2.0 4.5 ns
TSDDCK Input setup time, all inputs 2.0 ns
TSDCKD Input hold time, all inputs 2.0 ns
SD/SDIO Interface High-speed Mode
FSDHS_CLK SD high-speed device clock frequency 25 50 MHz
TSDHSDC_CLK SD high-speed device clock duty cycle 45 55 %
TSDHSCKO Clock to output delay, all outputs 2.2 13.8 ns
TSDHSDIVW Input valid data window 0.4 UI
SD/SDIO Interface SDR12 Mode
FSDSDR12_CLK 2 SD SDR12 device clock frequency 25 MHz
TDCSDSDR12_CLK SD SDR12 device clock duty cycle 30 70 %
TSDSDR12CKO Clock to output delay, all outputs 1.0 36.8 ns
TSDSDR12DCK Input setup time, all inputs 10.0 ns
TSDSDR12CKD Input hold time, all inputs 1.5 ns
SD/SDIO Interface SDR25/SDR50 Mode
FSDSDR_CLK SDR25 device clock frequency 25 50 MHz
SDR50 device clock frequency 25 100 MHz
TSDSDRDC_CLK SD SDR50/SDR25 device clock duty cycle 30 70 %
TSDSDRCKO Clock to output delay, all outputs 1.0 6.8 ns
TSDDDRCKD Input valid data window 0.4 UI
SD/SDIO Interface SDR104 Mode
FSDSDR104_CLK SDR104 device clock frequency 25 200 MHz
TDCSDSDR104_CLK SD SDR104 device clock duty cycle 30 70 %
TSDSDR104CKO Clock to output delay, all outputs 1.0 3.2 ns
TSDSDR104CKD Input valid data window 0.5 UI
SD/SDIO Interface DDR50 Mode
FSDDDR_CLK SD DDR50 device clock frequency 25 50 MHz
TDCSDDDR_CLK SD DDR50 device clock duty cycle 45 55 %
TSDDDRCKO Clock to output delay, data 1.0 6.8 ns
TSDDDRDCK Input valid data window 0.5 UI
TSDDDRCKD Input setup time, command 4.7 ns
TSDDDRIDCLK Input hold time, command 1.5 ns
TSDDDRCLK Clock to output delay, command 1.0 13.8 ns
  1. The test condition settings for SD/SDIO modes are: 12 mA drive strength, fast slew rate, and a 15 pF load. The OTAP delay (OTAP_DLY[5:0] ) test condition settings are: SD high-speed mode = 0x04, SD SDR25/50 mode = 0x03, SD SDR104 mode = 0x02, and SD DDR50 mode = 0x03.
  2. EMIO is supported in SD default speed mode and SDR12 mode.