Revision History

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)

Document ID
Release Date
1.1 English

The following table shows the revision history for this document.

Section Revision Summary
12/05/2022 Version 1.1
General Updated the following tables for production release of some of the speed grade/operating voltages of the VP1202 -2M (VCCINT = 0.80) in Vivado Design Suite v2022.2 v2.00.
Added overdrive specifications (where applicable) to Table 1 and Table 2.
Recommended Operating Conditions Added Note 7 for the -2LLI VCCINT (Low).
Available Speed Grades and Operating Voltages Added Note 5.
DC Characteristics Over Recommended Operating Conditions Updated the ICC_BATT conditions and values.
PMC JTAG and SelectMAP Updated Note 1 in Table 1 to include all transceivers when using AC-JTAG.
PMC Quad-SPI Controller Interface Updated the FQSPI_REFCLK maximum for Quad-SPI device clock frequency operating at ≤37.5 MHz (Loopback disabled) from 150 MHz to 300 MHz.
PMC SD/SDIO Controller Interface Added TSDDCK and TSDCKD to the table and revised the minimum value for TSDSDR12DCK to 10.0 ns.
PMC eMMC Controller Interface Added TEMMCDCK and TEMMCCKD.
Package Parameter Guidelines Removed VSVC2197 package from the list of packages for the VP1202.
Device Identification Revised the VP1202 IDCODE for production.
GTM Transceiver DC Input and Output Levels Updated the DVPPIN PAM4 maximum specification in Table 1. Also revised the VCMOUTDC conditions and equations. Added Table 3.
GTM Transceiver Performance Revised the GTM transceiver PAM4 maximum line rate.
GTM Transceiver PLL/Lock Time Adaptation Updated conditions for TLOCK.
GTM Transceiver Transmitter and Receiver Switching Characteristics Removed the PAM4 82.5 Gb/s sinusoidal jitter condition.
Table 2 Updated RXPPMTOL conditions and Note 1, and added Note 4.
GTM Transceiver Electrical Compliance Updated table with 106.25 Gb/s protocol information.
Table 1 Revised table and added Notes 1 and 2.
GTY and GTYP Transceiver DC Input and Output Levels Revised VCMOUTDC and VCMOUTAC equations. Updated values in Table 3.
GTY and GTYP Transceiver Performance Revised the GTYP maximum line rate.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated FTXIN and FRXIN.
Integrated Block for DCMAC Updated the -3/-2 (0.88V), -2 (0.80V), and -2 (0.70V) AXI4-Stream interface clock values.
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM) Added the -1 (0.70V) overdrive values for some of the frequencies in this topic.
5/02/2022 Version 1.0
Initial release. N/A