The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.
Symbol | Description 1, 2 | Device | Performance as a Function of Speed Grade and Operating Voltage (VCCINT) | Units | ||||
---|---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.70V (L) | ||||||
-3 | -2 | -1 | -2 | -1 | ||||
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM | ||||||||
TICKOFMMCM | Global clock input and output flip-flop with MMCM | XCVH1522 | 5.87 | 6.52 | 6.87 | 6.52 | 6.89 | ns |
XCVH1542 | 5.87 | 6.52 | 6.87 | 6.52 | 6.89 | ns | ||
XCVH1582 | 5.87 | 6.52 | 6.87 | 6.52 | 6.89 | ns | ||
XCVH1742 | 5.87 | 6.52 | 6.87 | 6.52 | 6.89 | ns | ||
XCVH1782 | 5.87 | 6.52 | 6.87 | 6.52 | 6.89 | ns | ||
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