High Bandwidth Memory Controller

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)

Document ID: DS960
Release Date: 2024-02-29
Revision: 1.4 English

The Versal Architecture and Product Data Sheet: Overview (DS950) lists the Versal HBM devices with integrated high-bandwidth memory (HBM).

Table 1. Maximum Performance for High Bandwidth Memory Controller
Symbol	Description	Performance as a Function of Speed Grade and Operating Voltage (V_{CCINT_IO_HBM})					Units
		0.88V (H)	0.80V (M)		0.80V (L)¹
		-3	-2	-1	-2	-1
F_ACLK	AXI interface clock maximum frequency	540	500	480	500	480	MHz
F_HBM	HBM maximum line rate interface to DRAM	3200	3200	3200	3200	3200	Mb/s
F_{BYPASS_MC}	HBM controller bypass mode maximum clock frequency	400	400	400	400	400	MHz
The HBM controller is powered by the V_{CCINT_IO_HBM} supply that operates at 0.80V in low (L) voltage operation. See Table 1.

Table 2. HBM Controller REF_CLK Maximum Frequency
Symbol	Description		Min	Max	Units
F_{HBM_REF_CLK} ¹	External reference clock frequency	LVDS	100	500	MHz
	External reference clock frequency	LVCMOS	100	125	MHz
	Internal reference clock frequency		100	200	MHz
The maximum reference clock frequency is not required for maximum HBM line rates.