Integrated Block for DCMAC

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)
Document ID
DS960
Release Date
2024-02-29
Revision
1.4 English

More information and documentation on solutions using the 600G channelized multirate Ethernet MAC (DCMAC) can be found in the Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) Product Guide (PG369). The Versal Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each Versal HBM device.

Table 1. Maximum Performance for DCMAC Designs
Symbol Description 1 Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
FRX_CORE_CLK Receive core clock 963.235 829.706 781.250 781.250 520.833 MHz
FTX_CORE_CLK Transmit core clock 963.235 829.706 781.250 781.250 520.833 MHz
FRX_AXIS_CLK Receive AXI4-Stream interface clock 529.779 456.338 390.625 429.688 260.417 MHz
FTX_AXIS_CLK Transmit AXI4-Stream interface clock 529.779 456.338 390.625 429.688 260.417 MHz
FRX_MAC_IF_CLK Receive MAC interface clock 481.618 414.853 390.625 390.625 260.417 MHz
FTX_MAC_IF_CLK Transmit MAC interface clock 481.618 414.853 390.625 390.625 260.417 MHz
FRX_SERDES_CLK Receiver serializer/deserializer clock 818.750 705.250 664.063 705.250 664.063 MHz
FTX_SERDES_CLK Transmit serializer/deserializer clock 818.750 705.250 664.063 705.250 664.063 MHz
FRX_ALT_SERDES_CLK Receive alternate serializer/deserializer clock 409.375 352.625 332.031 352.625 332.031 MHz
FTX_ALT_SERDES_CLK Transmit alternate serializer/deserializer clock 409.375 352.625 332.031 352.625 332.031 MHz
FTS_CLK Timestamp clock 350.000 350.000 350.000 350.000 350.000 MHz
FRX_FLEXIF_CLK Receive flex interface clock 496.212 427.424 390.625 390.625 312.500 MHz
FTX_FLEXIF_CLK Transmit flex interface clock 496.212 427.424 390.625 390.625 312.500 MHz
FAPB3_CLK APB3 clock 300.000 300.000 300.000 300.000 300.000 MHz
  1. Overclock rates are supported by faster speed grade devices (-3H and -2M).