Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM)

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)
Document ID
DS960
Release Date
2024-02-29
Revision
1.4 English

More information and documentation on solutions for PCI Express® designs can be found at PCI Express . The Versal Architecture and Product Data Sheet: Overview (DS950) lists how many blocks are in each Versal device.

Table 1. Maximum Performance for Streaming Mode Interface of Integrated Block for PCIe Rev. 5.0 with DMA and CCIX Rev. 1.1 (CPM5)
Symbol Description Mode Speed Grade and VCCINT_CPM5 1 Operating Voltage Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
PCIe Up To Gen3x16 With One Link With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
PCIe Up To Gen4x8 With Two Links With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
PCIe Up To Gen4x16 With One Link With 1024-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz
Up to Gen5x8 With Two Links Up To 1024-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz
CCIX Up To Gen3x16 With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 390 312 312 250 MHz
Overdrive N/A 390 N/A 312 N/A MHz
CCIX Up To Gen4x8 With One Link With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 390 312 312 250 MHz
Overdrive N/A 390 N/A 312 N/A MHz
CCIX Up To 20 Gb/s x8 With Two Links
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 156.125 156.125 156.125 156.125 N/A MHz
Overdrive N/A 156.125 N/A 156.125 N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 390 312 312 N/A MHz
Overdrive N/A 390 N/A 312 N/A MHz
CCIX Up To 25 Gb/s x8 With Two Links
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 195.312 195.312 N/A N/A N/A MHz
Overdrive N/A 195.312 N/A N/A N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 390 N/A N/A N/A MHz
Overdrive N/A 390 N/A N/A N/A MHz
CCIX Up To Gen4x16 With One Link
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 N/A N/A N/A N/A MHz
Overdrive N/A 390 N/A 312 N/A MHz
CCIX Up To Gen5x8 With Two Links
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz
FCPM_CHICLK_MAX CPM CHI clock maximum frequency 2 Standard 390 N/A N/A N/A N/A MHz
Overdrive N/A 390 N/A 312 N/A MHz
  1. See the Available Speed Grades and Operating Voltages for further information on the dual-voltage operation CPM5 supplies in overdrive mode (0.88V) or standard drive mode (0.70V/0.80V).
  2. The CHI clock domain is for the CHI interface that connects the coherent hub to the programmable logic.
Table 2. Maximum Performance for DMA Streaming Mode Interface of Integrated Block for PCIe Rev. 5.0 with DMA and CCIX Rev. 1.1 (CPM5)
Symbol Description Mode Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
PCIe® Up To Gen3x16 With One DMA instance With 512-bit Interface
FCPM_DMACLK_MAX CPM DMA to PL user clock maximum frequency Standard 433 400 300 250 250 MHz
Overdrive N/A 433 N/A 433 N/A MHz
PCIe Up To Gen4x8 With Two DMA Instances With 512-bit Interface
FCPM_DMACLK_MAX CPM DMA to PL (user) clock maximum frequency Standard 433 400 300 250 250 MHz
Overdrive N/A 433 N/A 433 N/A MHz
PCIe Up To Gen4x16 With One DMA Instance
FCPM_DMACLK_MAX CPM DMA to PL (user) clock maximum frequency Standard 433 N/A N/A N/A N/A MHz
Overdrive N/A 433 N/A 433 N/A MHz
CPM5 Configuration With Two Gen5x8 DMA Instances
FCPM_DMACLK_MAX CPM DMA to PL (user) clock maximum frequency Standard 433 N/A N/A N/A N/A MHz
Overdrive N/A 433 N/A 433 N/A MHz
Table 3. Maximum Performance for DMA Memory-Mapped AXI4 Mode Interface of Integrated Block for PCIe Rev. 5.0 with DMA and CCIX Rev. 1.1 (CPM5)
Symbol Description Mode Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-3 -2 -1 -2 -1
PCIe® Up To Gen3x16 With One DMA Instance With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
PCIe Up To Gen4x8 With Two DMA Instances With 512-bit Interface
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 250 250 250 250 MHz
Overdrive N/A 250 N/A 250 N/A MHz
PCIe® Up To Gen4x16 With One DMA Instance
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz
CPM5 Configuration With Two Gen5x8 Instances
FCPM_USERCLK_MAX CPM user clock maximum frequency Standard 250 N/A N/A N/A N/A MHz
Overdrive N/A 250 N/A 250 N/A MHz