Integrated High-speed Channelized Cryptography Engine

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)

Document ID: DS960
Release Date: 2024-02-29
Revision: 1.4 English

This section describes the maximum performance for the integrated high-speed channelized cryptography (HSC) engine configurations.

Table 1. High-Speed Channelized Cryptography Engine Performance
Symbol	Description	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)					Units
		0.88V (H)	0.80V (M)		0.70V (L)
		-3	-2	-1	-2	-1
F_{DEC_CORE_CLK}	Core clock for the decryption block	818.707	818.707	818.707	818.707	409.353	MHz
F_{ENC_CORE_CLK}	Core clock for the encryption block	818.707	818.707	818.707	818.707	409.353	MHz
F_{DEC_EGR_AXIS_CLK}	Egress AXI-S clock for the decryption block	409.353	409.353	409.353	409.353	204.677	MHz
F_{ENC_EGR_AXIS_CLK}	Egress AXI-S clock for the encryption block	409.353	409.353	409.353	409.353	204.677	MHz
F_{DEC_IGR_AXIS_CLK}	Ingress AXI-S clock for the decryption block	409.353	409.353	409.353	409.353	204.677	MHz
F_{ENC_IGR_AXIS_CLK}	Ingress AXI-S clock for the encryption block	409.353	409.353	409.353	409.353	204.677	MHz
F_{APB3_CLK}	APB3 clock	300.000	300.000	300.000	300.000	300.000	MHz