Recommended Operating Conditions

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)
Document ID
DS960
Release Date
2024-02-29
Revision
1.4 English
Table 1. Recommended Operating Conditions
Symbol Description 1 , 2, 3 Min Typ Max Units
VCCAUX Auxiliary power supply 1.455 1.500 1.545 V
VCCAUX_PMC PMC auxiliary power supply voltage 1.455 1.500 1.545 V
VCCAUX_SMON 4 PMC system monitor power supply relative to GND_SMON 1.455 1.500 1.545 V
VCC_BATT 5 Battery power supply to the battery-backed RAM and battery-backed real-time clock (RTC) 1.200 – 1.500 V
VCC_FUSE 6 eFUSE programming power supply 1.745 1.800 1.854 V
VCCINT PL primary power supply, low (L) voltage 0.676 0.700 0.724 V
PL primary power supply, mid (M) voltage 0.775 0.800 0.825 V
PL primary power supply, high (H) voltage 0.854 0.880 0.906 V
VCCINT_GT GTM primary power supply, low (L) and mid (M) voltage 0.775 0.800 0.825 V
GTM primary power supply, high (H) voltage 0.854 0.880 0.906 V
VCCINT_IO_HBM 7 High-bandwidth memory controller interface power supply, low (L) and mid (M) voltage 0.775 0.800 0.825 V
High-bandwidth memory controller interface power supply, high (H) voltage 0.854 0.880 0.906 V
VCC_CPM5 CPM5 primary power supply, low (L) voltage 0.676 0.700 0.724 V
CPM5 primary power supply, mid (M) voltage 0.775 0.800 0.825 V
CPM5 primary power supply, high (H) voltage 0.854 0.880 0.906 V
CPM5 primary power supply, overdrive voltage for higher CPM5 performance in -2LSE, 2LLE, -2MSE, and -2MLE devices 0.854 0.880 0.906 V
VCC_IO 7 XPIO power supply, low (L) and mid (M) voltage 0.775 0.800 0.825 V
XPIO power supply, high (H) voltage 0.854 0.880 0.906 V
VCCO 8

XPIO bank 7## output driver power supply

Includes VCCO of 1.0V, 1.1V, 1.2V, 1.35V, 1.5V at ±5%

 0.950 – 1.575 V

PSIO bank 5## power supplies

Includes VCCO of 1.8V, 2.5V at ±5%, and 3.3V at +3/–5%

 1.710 – 3.400 V
VCC_PMC 9 PMC primary power supply, low (L) voltage 0.676 0.700 0.724 V
PMC primary power supply, mid (M) voltage 0.775 0.800 0.825 V
PMC primary power supply, high (H) voltage 0.854 0.880 0.906 V
PMC primary power supply, overdrive voltage for higher PMC performance in -2LSE, 2LLE, -2MSE, -2MLE, -2MSI, and -2MLI devices 0.854 0.880 0.906 V
VCC_PSFP PS full-power domain power supply, low (L) voltage 0.676 0.700 0.724 V
PS full-power domain power supply, mid (M) voltage 0.775 0.800 0.825 V
PS full-power domain power supply, high (H) voltage 0.854 0.880 0.906 V
PS full-power domain power supply, overdrive voltage for higher PS performance in -2LSE, 2LLE, -2MSE, and -2MLE devices 0.854 0.880 0.906 V
VCC_PSLP PS low-power domain power supply, low (L) voltage 0.676 0.700 0.724 V
PS low-power domain power supply, mid (M) voltage 0.775 0.800 0.825 V
PS low-power domain power supply, high (H) voltage 0.854 0.880 0.906 V
PS low-power domain power supply, overdrive voltage for higher PS performance in -2LSE, 2LLE, -2MSE, and -2MLE devices 0.854 0.880 0.906 V
VCC_RAM PL RAM and clocking network power supply, low (L) and mid (M) voltage 0.775 0.800 0.825 V
PL RAM and clocking network power supply, high (H) voltage 0.854 0.880 0.906 V
VCC_SOC 7 Network on Chip (NoC) and DDR memory controller power supply, low (L) and mid (M) voltage 0.775 0.800 0.825 V
NoC and DDR memory controller power supply, high (H) voltage 0.854 0.880 0.906 V

VGTYP_AVCC 10

GTYP transceiver primary analog power supply

 0.892 0.920 0.948 V
VGTM_AVCC 10

GTM transceiver primary analog power supply

 0.892 0.920 0.948 V

VGTYP_AVCCAUX 10

VGTM_AVCCAUX 10

GTYP (or GTM) transceiver auxiliary analog (PLL) power supply

 1.455 1.500 1.545 V

VGTYP_AVTT 10

VGTM_AVTT 10

GTYP (or GTM) transceiver termination power supply

 1.164 1.200 1.236 V

VGTYP_AVTTRCAL 10

VGTM_AVTTRCAL 10

GTYP (or GTM) transceiver analog resistor calibration power supply

 1.164 1.200 1.236 V
VIN 11,12 I/O input voltage for PSIO and XPIO banks –0.200 – VCCO + 0.200 V
VCC_HBM Supply voltage for the high-bandwidth memory (HBM) 1.164 1.200 1.236 V
VCCO_HBM I/O supply voltage for the high-bandwidth memory 1.164 1.200 1.236 V
VCCAUX_HBM Auxiliary supply voltage for the high-bandwidth memory 2.425 2.500 2.575 V
IIN 13 Maximum current through any PL, PMC, or PS pin in a powered or unpowered bank when forward biasing the clamp diode – – 10 mA
Tj Junction temperature operating range for extended (E) temperature devices 14 0 – 100 °C
Junction temperature operating range for the integrated HBM 15 0 – 105 °C
Junction temperature operating range for eFUSE programming 14 –40 – 125 °C
  1. All voltages are relative to GND and in relation to the BGA package ball.
  2. For the design of the power distribution system consult the Versal Adaptive SoC PCB Design User Guide (UG863) and Power Design Manager (PDM) tool (download at www.xilinx.com/power).
  3. Each voltage listed requires decoupling as described in the Versal Adaptive SoC PCB Design User Guide (UG863). Refer to the Power Design Manager (PDM) tool (download at www.xilinx.com/power) for design specific decoupling recommendations.
  4. VCCAUX_SMON must be connected to VCCAUX_PMC . See Versal Adaptive SoC System Monitor Architecture Manual (AM006) for VCCAUX_SMON information and filter considerations.
  5. When the battery-backed RAM and the real-time clock are not used, connect to GND.
  6. VCC_FUSE must be within the recommended operating conditions during eFUSE programming. When VCC_FUSE is not used, connect to GND.
  7. VCCINT_IO_HBM and VCC_IO must be connected to VCC_SOC.
  8. For XPIO operation, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010). PSIO includes PMC dedicated I/O banks, PMC MIO banks, and LPD MIO banks. For PSIO operation, see the Versal Adaptive SoC Technical Reference Manual (AM011) .
  9. The physical unclonable function (PUF) is only supported when using a nominal VCC_PMC of 0.70V . Refer to the Versal Adaptive SoC Security Manual (UG1508) in the Design Security Lounge for detailed information on PUF usage, including a VCC_PMC 0.70V solution for mid, high, and overdrive. When using a VCC_PMC 0.70V solution, performance is reduced for functions based on the VCC_PMC. The PUF is not supported in -3H devices.
  10. Each voltage listed requires filtering as described in the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002) or the Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017) . The noise beyond the recommended operating conditions at the power pins must not exceed 10 mVpp over the band from 10 kHz to 80 MHz.
  11. The lower absolute voltage specification always applies.
  12. In XPIO banks, VIN overshoot above VCCO and undershoot below GND can reduce the performance of VREF-based receivers within the same nibble.
  13. A total of 200 mA per bank should not be exceeded.
  14. Junction temperature specification is in relation to the absolute value reported by the PMC system monitor.
  15. The integrated HBM junction operating temperature is in relation to the value of the temperature sensor inside the integrated HBM. The Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) describes how to access the HBM stack temperature.