FPGA Resource Information

Alveo U200 and U250 Data Center Accelerator Cards Data Sheet (DS962)

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1.5 English

The Xilinx Alveo U200 and U250 accelerator cards are custom-built UltraScale+ FPGAs that run optimally (and exclusively) on the Alveo architecture. The Alveo U200 card uses the XCU200 FPGA and the Alveo U250 card uses the XCU250 FPGA, both of which use Xilinx stacked silicon interconnect (SSI) technology to deliver breakthrough FPGA capacity, bandwidth, and power efficiency. This technology allows for increased density by combining multiple super logic regions (SLRs). The XCU200 comprises three SLRs and the XCU250 comprises four SLRs. Both devices connect to 16 lanes of PCI Express® that can operate up to 8 GT/s (Gen3). Both devices connect to four DDR4 16 GB, 2400 MT/s, 64-bit with error correcting code (ECC) DIMMs for a total of 64 GB of DDR4. Both devices connect to two QSFP28 connectors with associated clocks generated on board. The following figures show the SLR regions along with the PCIe, DDR4 and QSFP28 connections for the Alveo U200 and U250 cards. The U250 card has four SLRs while the U200 card has three SLRs.

Figure 1. Floorplan of the XCU200 Device
Figure 2. Floorplan of the XCU250 Device

For customers using the Vitis™ application acceleration development flow, a platform is created that manages the PCIe interface, data transfers, and card status information. It also remotely loads kernels and performs several functions that greatly simplify developing an application. This platform is part of the static region (an area of the FPGA that is not reconfigurable). This platform consumes resources from the available resources listed in Table 1. The specific amount of resources depends on which platform, and even which version of a platform is used. This information is available in the Alveo Data Center Accelerator Card Platforms User Guide (UG1120).

For developing applications, refer to the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).