FPGA Resource Information

Alveo U55C Data Center Accelerator Cards Data Sheet (DS978)

Document ID
DS978
Release Date
2022-09-01
Revision
1.1 English

The Xilinx Alveo U55C accelerator card includes a custom-built UltraScale+ FPGA that runs optimally (and exclusively) on Alveo architecture. The Alveo U55C card features the XCU55C FPGA, which uses Xilinx stacked silicon interconnect (SSI) technology to deliver breakthrough FPGA capacity, bandwidth, and power efficiency. This technology allows for increased density by combining multiple super logic regions (SLRs).

The following figure shows the three SLR regions of the XCU55C along with the connections for PCIe and QSFP. The HBM2 is co-located on the XCU55C device and connects directly to SLR0.

Figure 1. Floorplan of the XCU55C Device with Dual QSFP Connection