Functional Interfaces

Kria K26 SOM Data Sheet (DS987)

Document ID
DS987
Release Date
2022-03-15
Revision
1.2 English

The K26 SOM provides a combination of fixed and user-defined functional interfaces. Each interface is implemented with one of the major systems within the MPSoC. The following table is a summary of the interfaces, and system association (PS or PL), with a description of their use.

Table 1. Interfaces Summary
Interface Physical Location Linked Subsystem Functional Description
QSPI

MIO bank 500

MIO[5:0]
PS SOM QSPI memory
SD

MIO bank 500

MIO[23:13]
PS SOM eMMC memory, MIO[22:13] = eMMC, MIO[23] = eMMC reset
I2C

MIO bank 500

MIO[25:24]
PS SOM power management, EEPROM, and carrier card extensible I2C bus
SPI

MIO bank 500

MIO[11:9], MIO[6]
PS Isolated SPI interface for TPM 2.0 security module
Power management

MIO bank 501

MIO[34:32]
PS Fixed PMU SOM based power management
Power management MIO bank 501 MIO[31]. MIO[35] PS MIO35_WD_OUT and MIO31_SHUTDOWN: Optional power management control signals for use by CC designer
MIO – user defined I/O

MIO bank 501

MIO[30:26], MIO[51:38]
PS 19 user-defined multiplexed CPU connected I/O pins
MIO – user defined I/O

MIO Bank 502

MIO[77:52]
PS 26 user-defined multiplexed CPU connected I/O pins
DDR memory controller MIO bank 504 PS SOM DDR4 memory
HDA HDIO bank 45 PL 21 user-defined high-density input/output pins
HDB HDIO bank 43 PL 24 user-defined high-density input/output pins
HDC HDIO bank 44 PL 24 user-defined high-density input/output pins
HPA HPIO bank 66 PL 16 user-defined high-performance input/output differential pin pairs
HPB HPIO bank 65 PL 21 user-defined high-performance input/output differential pin pairs
HPC HPIO bank 64 PL 21 user-defined high-performance input/output differential pin pairs
PS-GTR transceivers PS GTR 505 PS Four lanes of user-defined high-speed serial transceivers
GTH transceivers GTH Quad PL Four lanes of user-defined high-speed serial transceivers

The K26 SOM provides a large number of flexible user-defined I/O that can be configured for various I/O standards and voltage levels. Voltage levels for each HDIO and HPIO bank can be customized by the SOM carrier card to provide the application-required voltage rails to the corresponding I/O banks. See the Supported I/O Standards section for the I/O voltage rail pin definitions and corresponding decoupling requirements.

The K26 SOM provides PS-GTR and GTH transceivers to implement various high-speed protocols. The supported protocols are listed in the protocol tables of the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925), and are described in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) and Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137). The transceivers are configured via the Vivado® Design Suite.