HDIO: HDA, HDB, and HDC Banks

Kria K26 SOM Data Sheet (DS987)

Document ID
DS987
Release Date
2022-03-15
Revision
1.2 English

This section describes the high-density I/O (HDIO) banks. The HDIO bank HDA (bank 45) is accessible through the SOM240_1 connector. HDIO banks HDB (bank 43) and HDC (bank 44) are accessible through the SOM240_2 connector.

  • The HDA bank supports 21 single-ended signals HDA[20:0]. Three signals (HDA00_CC, HDA08_CC, and HDA16_CC) are clock-capable inputs available on the MPSoC.
  • The HDB and HDC bank supports 24 single-ended signals HDx[23:0]. Three signals (HDx00_CC, HDx08_CC, and HDx16_CC) are clock-capable inputs available on the MPSoC.
  • The maximum data rate supported on HDIO signals is 250 Mb/s.
  • VCCO for the HD(x) bank is supplied by the carrier card through the VCCO_HD(x) pins where x = A, B, or C.

HDIO bank connections are listed in the following table.

Table 1. HDIO Bank Connections
HDIO Bank Connector HDIO Signals Clock-capable Pins VCCO
HDA bank 45 SOM240_1 HDA[20:00] HDA00, HDA08, HDA16 VCCO_HDA
HDB bank 43 SOM240_2 HDB[23:00] HDB00, HDB08, HDB16 VCCO_HDB
HDC bank 44 SOM240_2 HDC[23:00] HDC00, HDC08, HDC16 VCCO_HDC