HPIO: HPA, HPB, and HPC Banks

Kria K26 SOM Data Sheet (DS987)

Document ID
DS987
Release Date
2022-03-15
Revision
1.2 English

This section describes the high-performance I/O (HPIO) banks. The HPIO bank HPA (bank 66) is accessible through the SOM240_1 connector. The HPIO banks HPB (bank 65) and HPC (bank 64) are accessible through the SOM240_2 connector.

  • All signals in the HPIO banks are routed as differential pairs. Each HPIO bank has a separate differential global clock input, namely HPA_CLK0_P/N, HPB_CLK0_P/N, and HPC_CLK0_P/N.
  • The maximum data rate supported on HPIO signals is 2.5 Gb/s.
  • VCCO for the HP(x) bank is supplied by the carrier card through the VCCO_HP(x) pins where x = A, B, C.

HPIO bank connections are listed in the following table.

Table 1. HPIO Bank Connections
HPIO Bank Connector HPIO Signals Clock-capable Pins VCCO
HPA bank 66 SOM240_1 HPA[14:00]_P/N, HPA_CLK0_P/N HPA_CLK0_P/N VCCO_HPA
HPB bank 65 SOM240_2 HPB[19:00]_P/N, HPB_CLK0_P/N HPB_CLK0_P/N VCCO_HPB
HPC bank 64 SOM240_2 HPC[19:00]_P/N, HPC_CLK0_P/N HPC_CLK0_P/N VCCO_HPC

MIPI Support

The differential signal pairs in HPIO banks HPA, HPB, and HPC are organized to support MIPI links with up to four lanes. A four lane MIPI link requires five differential HPIO signals, with the first signal pair supporting a clock-capable signal pair. Bank HPA can support three MIPI links. Banks HPB and HPC can support four MIPI links each. The following table lists the MIPI links.

Table 2. Bank Organization
  CLK CSI0 CSI1 CSI2 CSI3
MIPIA0 HPA00_CC HPA01 HPA02 HPA03 HPA04
MIPIA1 HPA05_CC HPA06 HPA07 HPA08 HPA09
MIPIA2 HPA10_CC HPA11 HPA12 HPA13 HPA14
MIPIB0 HPB00_CC HPB01 HPB02 HPB03 HPB04
MIPIB1 HPB05_CC HPB06 HPB07 HPB08 HPB09
MIPIB2 HPB10_CC HPB11 HPB12 HPB13 HPB14
MIPIB3 HPB15_CC HPB16 HPB17 HPB18 HPB19
MIPIC0 HPC00_CC HPC01 HPC02 HPC03 HPC04
MIPIC1 HPC05_CC HPC06 HPC07 HPC08 HPC09
MIPIC2 HPC10_CC HPC11 HPC12 HPC13 HPC14
MIPIC3 HPC15_CC HPC16 HPC17 HPC18 HPC19