The industrial grade Kria K26I SOM (K26I) uses an exclusive Zynq UltraScale+ MPSoC with the speed/temperature grade of -2LI (VCCINT = 0.72V). This device is not specified in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925). For some of the Zynq UltraScale+ MPSoC blocks, the -2LI (VCCINT = 0.72V) and -2LE (VCCINT = 0.72V) have the same switching characteristics. For the switching characteristics of -2LI that are the same as the -2LE, refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925). For switching characteristics that are not the same as those in the data sheet and are relevant to the K26I SOM, refer to the following tables.
Symbol | Description | -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) | Units |
---|---|---|---|
Maximum Frequency | |||
FMAX_WF_NC | Block RAM (WRITE_FIRST and NO_CHANGE modes) | 516 | MHz |
FMAX_RF | Block RAM (READ_FIRST mode) | 495 | MHz |
FMAX_FIFO | FIFO in all modes without ECC | 516 | MHz |
FMAX_ECC | Block RAM and FIFO in ECC configuration without PIPELINE | 460 | MHz |
Block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in WRITE_FIRST or NO_CHANGE mode | 516 | MHz | |
TPW 1 | Minimum pulse width | 578 | ps |
Block RAM and FIFO Clock-to-Out Delays | |||
TRCKO_DO | Clock CLK to DOUT output (without output register) | 1.53 | ns, Max |
TRCKO_DO_REG | Clock CLK to DOUT output (with output register) | 0.44 | ns, Max |
|
Symbol | Description | -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) | Units |
---|---|---|---|
Maximum Frequency | |||
FMAX | UltraRAM maximum frequency with OREG_B = True | 495 | MHz |
FMAX_ECC_NOPIPELINE | UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = True | 303 | MHz |
FMAX_NOPIPELINE | UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = False | 389 | MHz |
TPW 1 | Minimum pulse width | 832 | ps |
TRSTPW | Asynchronous reset minimum pulse width. One cycle required | 1 clock cycle | |
|
Symbol | Description | -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) 1 | Units |
---|---|---|---|
Maximum Frequency | |||
FMAX | With all registers used | 600 | MHz |
FMAX_PATDET | With pattern detector | 524 | MHz |
FMAX_MULT_NOMREG | Two register multiply without MREG | 413 | MHz |
FMAX_MULT_NOMREG_PATDET | Two register multiply without MREG with pattern detect | 371 | MHz |
FMAX_PREADD_NOADREG | Without ADREG | 423 | MHz |
FMAX_NOPIPELINEREG | Without pipeline registers (MREG, ADREG) | 304 | MHz |
FMAX_NOPIPELINEREG_PATDET | Without pipeline registers (MREG, ADREG) with pattern detect | 280 | MHz |
|
Symbol | Description | Output Divider | -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) | Units | |
---|---|---|---|---|---|
FGTHMAX | GTH maximum line rate | 10.3125 | Gb/s | ||
FGTHMIN | GTH minimum line rate | 0.5 | Gb/s | ||
Min | Max | ||||
FGTHCRANGE | CPLL line rate range 1 | 1 | 4 | 8.5 | Gb/s |
2 | 2 | 4.25 | Gb/s | ||
4 | 1 | 2.125 | Gb/s | ||
8 | 0.5 | 1.0625 | Gb/s | ||
16 | N/A | Gb/s | |||
Min | Max | ||||
FGTHQRANGE1 | QPLL0 line rate range 2 | 1 | 9.8 | 10.3125 | Gb/s |
2 | 4.9 | 8.15 | Gb/s | ||
4 | 2.45 | 4.075 | Gb/s | ||
8 | 1.225 | 2.0375 | Gb/s | ||
16 | 0.6125 | 1.0118 | Gb/s | ||
Min | Max | ||||
FGTHQRANGE2 | QPLL1 line rate range 3 | 1 | 8.0 | 10.3125 | Gb/s |
2 | 4.0 | 6.5 | Gb/s | ||
4 | 2.0 | 3.25 | Gb/s | ||
8 | 1.0 | 1.625 | Gb/s | ||
16 | 0.5 | 0.8125 | Gb/s | ||
Min | Max | ||||
FCPLLRANGE | CPLL frequency range | 2 | 4.25 | GHz | |
FQPLL0RANGE | QPLL0 frequency range | 9.8 | 16.375 | GHz | |
FQPLL1RANGE | QPLL1 frequency range | 8 | 13 | GHz | |
|
Symbol | Description 1 | Data Width Conditions (Bit) | -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) 2 | Units | |
---|---|---|---|---|---|
Internal Logic | Interconnect Logic | ||||
FTXOUTPMA | TXOUTCLK maximum frequency sourced from OUTCLKPMA | 322.266 | MHz | ||
FRXOUTPMA | RXOUTCLK maximum frequency sourced from OUTCLKPMA | 322.266 | MHz | ||
FTXOUTPROGDIV | TXOUTCLK maximum frequency sourced from TXPROGDIVCLK | 511.719 | MHz | ||
FRXOUTPROGDIV | RXOUTCLK maximum frequency sourced from RXPROGDIVCLK | 511.719 | MHz | ||
FTXIN | TXUSRCLK 3 maximum frequency | 16 | 16, 32 | 322.266 | MHz |
32 | 32, 64 | 322.266 | MHz | ||
20 | 20, 40 | 257.813 | MHz | ||
40 | 40, 80 | 257.813 | MHz | ||
FRXIN | RXUSRCLK 3 maximum frequency | 16 | 16, 32 | 322.266 | MHz |
32 | 32, 64 | 322.266 | MHz | ||
20 | 20, 40 | 257.813 | MHz | ||
40 | 40, 80 | 257.813 | MHz | ||
FTXIN2 | TXUSRCLK2 3 maximum frequency | 16 | 16 | 322.266 | MHz |
16 | 32 | 161.133 | MHz | ||
32 | 32 | 322.266 | MHz | ||
32 | 64 | 161.133 | MHz | ||
20 | 20 | 322.266 | MHz | ||
20 | 40 | 161.133 | MHz | ||
40 | 40 | 257.813 | MHz | ||
40 | 80 | 128.906 | MHz | ||
FRXIN2 | RXUSRCLK2 3 maximum frequency | 16 | 16 | 322.266 | MHz |
16 | 32 | 161.133 | MHz | ||
32 | 32 | 322.266 | MHz | ||
32 | 64 | 161.133 | MHz | ||
20 | 20 | 257.813 | MHz | ||
20 | 40 | 128.906 | MHz | ||
40 | 40 | 257.813 | MHz | ||
40 | 80 | 128.906 | MHz | ||
|