- PS-GTR transceivers are accessible through the SOM240_1 connector.
- GTR_DP[3:0]_M2C_P/N pins are transmit signals from the MPSoC.
- GTR_DP[3:0]_C2M_P/N pins are receive signals to the MPSoC.
- GTR_REFCLK[3:0]_P/N pins are REFCLKs inputs to the MPSoC.
- PS-GTR transceivers support a maximum transfer rate of 6 Gb/s over each lane.
- The carrier cards must supply the appropriate clock signals as required by the application.
- The PS-GTR transceivers support the following protocols:
- PCIe Gen1/2
- Serial ATA (SATA) 3.1
- USB 3.0
- DisplayPort 1.2
- 10M/100M/1G Ethernet MAC (GEM)