Processing System

Kria K26 SOM Data Sheet (DS987)

Document ID
DS987
Release Date
2022-03-15
Revision
1.2 English

This section outlines the processing system (PS) resources. It includes:

APU
Arm® Cortex®-A53 based application processing unit (APU) consisting of quad-core Cortex-A53 processors with an FMAX = 1333 MHz, L2 cache, SIMD, VFP4 floating point, and cryptography extensions.
RPU
Arm Cortex-R5F based real-time processing unit (RPU) consisting of dual-core Cortex-R5F processors with floating point unit support with an FMAX = 533 MHz, able to operate in stand-alone and lock-step functions.
PMU
Platform management unit for dedicated SOM power and subsystem management functions.
Dynamic memory controller (DDRC)
DDR4 memory controller with configurable quality-of-service configuration capabilities.
GPU
Arm Mali™ -400 MP2 based graphics processing unit with an FMAX = 600 MHz.
System Monitor
Built-in analog-digital-converter (ADC) with threshold checks for monitoring and reporting power supply and temperature conditions.
RTC
Real-time clock for maintaining an accurate time base with optional battery backup through a carrier card pin.

The PS provides access to a number of integrated peripherals through multiplexed input/output (MIO) banks. The MPSoC has a total of three MIO banks. The SOM uses the first bank for the on-board peripherals, while the other two MIO banks are customizable and available through the SOM connector interface. All three MIO banks are powered by the SOM with a 1.8V power rail.

Refer to the MIO Interfaces table in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information on MIO usage for Zynq UltraScale+ MPSoCs. MIO mapping must comply with the Zynq UltraScale+ MPSoC design constraints and requirements.