Sideband Signals

Kria K26 SOM Data Sheet (DS987)

Document ID
Release Date
1.2 English

The sideband signals consist of power, processor, and configuration signals. VCCO for sideband signals is 1.80V.

The JTAG signals JTAG_TCK_C2M, JTAG_TMS_C2M, JTAG_TDI_C2M, and JTAG_TDO_M2C connect to the SOM Zynq UltraScale+ MPSoC JTAG port.
The PS_REF_CLK input is connected to a 33.33 MHz oscillator.
The PS RTC inputs are connected to a 32.768 kHz crystal.
The I2C signals I2C_SCK and I2C_SDA connect to an I2C master on MIO bank 500 of the SOM Zynq UltraScale+ MPSoC. The I2C I/O standard is 1.8V.
The connector PS_MODE[3:0] pins connect to the SOM Zynq UltraScale+ MPSoC PS_MODE pins. All mode pins are pulled High to 1.8V through a resistor on the SOM.
The carrier card boot mode is required to set the PS_MODE pins to a valid boot mode as defined in the Zynq UltraScale+ Device Technical Reference Manual (UG1085). To configure a PS_MODE pin to a logic 1, the pin must be left floating, to configure a logic 0, the PS_MODE pin must be connected to GND with a 0Ω resistor.
During power up, a voltage monitor keeps PS_POR_L asserted (Low) until all SOM power rails are stabilized. Afterward, PS_POR_L is released and the boot process starts. A carrier card can use PS_POR_L to reset any on-board devices. The carrier card can also force PS_POR_L Low to extend the reset during power on to reset the system at any time.
The PS_SRST_C2M_L pin connects to PS_SRST_B signal on the SOM Zynq UltraScale+ MPSoC. PS_SRST_B input signal to the Zynq UltraScale+ MPSoC is the system reset signal, and it is commonly used during debug. PS_SRST_C2M_L is pulled High to 1.8V on the SOM.