Clock - 1.0 English

Versal ACAP CIPS Verification IP (DS996)

Document ID
DS996
Release Date
2021-07-14
Version
1.0 English
APIs Inputs Outputs
pl_gen_clock

This API generates the PS to PL clocks with the frequency in MHz as the input along with the clock port number.

For example: versal_cips_0.inst.PS9_VIP_inst.inst.pl_gen_clock(0,100) → Generates PMCRCLKCLK[0] with 100 MHz frequency

[1:0] clk_num:
  • 2’b00 → PMCRCLKCLK[0]
  • 2’b01 → PMCRCLKCLK[1]
  • 2’b10 → PMCRCLKCLK[2]
  • 2’b11 → PMCRCLKCLK[3]

[31:0] freq_in_mhz: This can be any integer value

None
cpm_osc_clk_div2_gen_clock

This API generates clock on CPMOSCCLKDIV2 port of CPM, and the frequency is in MHz which is passed as input .

For example:

versal_cips_0.inst.PS9_VIP_inst.inst. cpm_osc_clk_div2_gen_clock(100) → Generates 100 MHz frequency on CPMOSCCLKDIV2 port

[31:0] freq_in_mhz: This can be any integer value None
cpm_gen_clock

This API generates clock on LPDCPMINREFCLK port of CPM and the frequency is in MHz which is passed as input .

For example:

versal_cips_0.inst.PS9_VIP_inst.inst. cpm_gen_clock(100) → Generates 100 MHz frequency on LPDCPMINREFCLK port

[31:0] freq_in_mhz: This can be any integer value None