Features - 1.0 English

Versal ACAP CIPS Verification IP (DS996)

Document ID
DS996
Release Date
2021-07-14
Version
1.0 English
  • Narrow transfers are supported for 32/64-bit transfers.
  • 8/16/32-bit width registers are supported.
  • ACE interface supports only AXI4 traffic, all sideband signals are ignored.
  • ACP interface supports limited AXI4 features.
    • For ACP, AxSIZE is tied to 4 (128-bit).
    • AxBURST = 1 (only INCR is supported).
  • PL clock/PL reset/PS-PL/PL-PS interrupts supported in API.
  • On CCI ports,
    • No coherency supported.
    • Support for striping across the four CCI interfaces on 1 KB, 2 KB, and 4 KB boundaries.
    • Only one CCI port can be accessed at a time.
    • Bus split is not supported.

    For example, CCI boundary configured for 1K,

    • AWADDR: 3FC, AWLEN:1 (2 beats), AWSIZE: 2 (32-bit), AWBURST: INCR.

    This transaction accesses addresses from 3FC to 3FC + (2 × 4) that is, 3FC to 404. The above transaction crosses the 1K boundary and it cannot be used by the CCI decoding logic/DeMUX. The current Versal ACAP CIPS VIP can take care of the initiated transactions which are not crossing CCI boundaries.

    This means:

    • Transaction-1: AWADDR: 3FC, AWLEN:0 (1 beat), AWSIZE: 2 (32-bit), AWBURST: INCR
    • Transaction-2: AWADDR: 400, AWLEN:0 (1 beat), AWSIZE: 2 (32-bit), AWBURST: INCR
    Tip: If there is a HANG in simulation,
    • Check if routing configuration is provided before the start of traffic.
    • When a different master tries to access the same slave, ensure to disable the earlier routing configuration and enable the new routing configuration.
    • Check VIP and AXI interfaces are connected to the single clock source.