Functional Description - 1.0 English

The Versal ACAP CIPS VIP is used to check the Versal ACAP CIPS-based BD design integrity to initiate AXI traffic on NoC and PL AXI ports.

The clock and reset needs to be provided to the Versal ACAP CIPS VIP. The versal_cips_ps_vip_clk is a VIP clock and it needs to be driven by a valid clock source (the same clock that is driven to the AXI4 interfaces). Reset to the Versal ACAP CIPS VIP is active-Low.

The following shows the example code for driving clock and reset:

force tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.versal_cips_ps_vip_clk = clock_source;
tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.por_reset(0);
repeat(20)@(posedge clock_source); 
tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.por_reset(1);

The Versal ACAP CIPS VIP has two internal AXI masters named R5_API and A72_API. These AXI4 masters are exercised through the APIs in the Application Programming Interfaces.

The Versal ACAP CIPS VIP models an OCM memory with supporting address range (0xFFFC_0000–0xFFFF_FFFF).

The Versal ACAP CIPS VIP implements the register space.

• Functional aspects of these registers are not modeled.
• Default values of the registers can be read.
• Error response is not modeled for register space.

If AXI SLVERR response for a particular PS register address range is expected, Versal ACAP CIPS VIP returns the SLVERR response.

set_param cips.enablePSVIPsimulation 0

The following table shows the available ports to debug in the Versal ACAP CIPS VIP.

The following figure shows the detailed architecture for the VIP logic.

Figure 1. Versal ACAP CIPS VIP Architecture