Functional Description - 1.0 English

Versal ACAP CIPS Verification IP (DS996)

Document ID
DS996
Release Date
2021-07-14
Version
1.0 English

The Versal ACAP CIPS VIP is used to check the Versal ACAP CIPS-based BD design integrity to initiate AXI traffic on NoC and PL AXI ports.

The clock and reset needs to be provided to the Versal ACAP CIPS VIP. The versal_cips_ps_vip_clk is a VIP clock and it needs to be driven by a valid clock source (the same clock that is driven to the AXI4 interfaces). Reset to the Versal ACAP CIPS VIP is active-Low.

The following shows the example code for driving clock and reset:

force tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.versal_cips_ps_vip_clk = clock_source;
tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.por_reset(0);
repeat(20)@(posedge clock_source); 
tb_top.DUT.design_1_i.versal_cips_0.inst.PS9_VIP_inst.inst.por_reset(1);

The Versal ACAP CIPS VIP has two internal AXI masters named R5_API and A72_API. These AXI4 masters are exercised through the APIs in the Application Programming Interfaces.

The Versal ACAP CIPS VIP models an OCM memory with supporting address range (0xFFFC_00000xFFFF_FFFF).

The Versal ACAP CIPS VIP implements the register space.

  • Functional aspects of these registers are not modeled.
  • Default values of the registers can be read.
  • Error response is not modeled for register space.

If AXI SLVERR response for a particular PS register address range is expected, Versal ACAP CIPS VIP returns the SLVERR response.

The following table shows the available ports to debug in the Versal ACAP CIPS VIP.

Table 1. Debug Port Names
GUI Name Actual VIP Port Name
M_AXI_FPD MAXIGP0
M_AXI_LPD MAXIGP2
N/A OCM
N/A IFPSCPMCFG
FPD_AXI_NOC_0 IFPSNOCNCIAXI0
FPD_AXI_NOC_1 IFPSNOCNCIAXI1
N/A IFPSNOCPCIAXI0
N/A IFPSNOCPCIAXI1
FPD_CCI_NOC_0 IFPSNOCCCIAXI0
FPD_CCI_NOC_1 IFPSNOCCCIAXI1
FPD_CCI_NOC_2 IFPSNOCCCIAXI2
FPD_CCI_NOC_3 IFPSNOCCCIAXI3
NOC_LPD_AXI_0 IFPSNOCRPUAXI0
PMC_NOC_AXI_0 IFPMCNOCAXI0
N/A IFPSCPMPCIE
S_AXI_FPD SAXIGP0
S_AXI_GP2 SAXIGP2
S_AXI_LPD SAXIGP4
S_ACP_FPD SAXIACP
S_ACE_FPD SACEFPD
NOC_FPD_AXI_0 IFNOCPSNCIAXI0
NOC_FPD_AXI_1 IFNOCPSNCIAXI1
NOC_FPD_CCI_0 IFNOCPSCCIAXI0
NOC_FPD_CCI_1 IFNOCPSCCIAXI1
NOC_PMC_AXI_0 IFNOCPMCAXI0
N/A IFNOCPSPCIAXI0
N/A IFCPMPSAXI0
N/A IFCPMPSAXI1

The following figure shows the detailed architecture for the VIP logic.

Figure 1. Versal ACAP CIPS VIP Architecture