IP Facts - 1.0 English

Versal ACAP CIPS Verification IP (DS996)

Document ID
DS996
Release Date
2021-07-14
Version
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal ACAP
Supported User Interfaces AXI4
Resources Not Provided
Provided with Core
Design Files Not Provided
Example Design System Verilog
Test Bench N/A
Constraints File N/A
Simulation Model System Verilog
Supported S/W Driver 2 N/A
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 75889
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.
  3. To take advantage of all the features of this IP, you need simulators that support advanced simulation capabilities.
  4. To use the virtual part of the AXI Verification IP, the IP must be in a Verilog hierarchy.