Limitations - 1.0 English

Versal ACAP CIPS Verification IP (DS996)

Document ID
DS996
Release Date
2021-07-14
Version
1.0 English

Address decoding is not modeled inside the Versal ACAP CIPS VIP. Therefore, routing configuration needs to be provided through API before initiating the traffic.

The entire Versal ACAP CIPS VIP works in a single clock domain (that is, all the slave and masters of Versal ACAP CIPS VIP work on the same frequency).

All of the Versal ACAP CIPS VIP AXI4 interface widths are static (that is, Address and Data widths cannot be changed through the CIPS GUI). If you attempt to change the widths, the behavior is undefined.

The following features are not supported:

  • Versal ACAP CIPS VIP does not handle any configuration information passed through the GUI, except enable and disable of PL AXI and NoC interfaces.
  • Versal ACAP CIPS VIP does not model any AXI4 path delays.
  • No AXI4 ID support.
  • CPM5 is not supported.
  • QoS (AxQOS) is not supported.
  • Cache coherency is not supported.
  • Exclusive Access (AxLOCK) is not supported.
  • Bufferability (AxCACHE) is not supported.
  • AxREGION is not supported.
  • Latency Modeling for OCM/REG is not supported.
  • ACELITE/NPI are not modeled.
  • Interconnect arbitration is not modeled as per the RTL.
  • Outstanding transactions are not supported for AXI4 interfaces.
  • Low power modeling is not supported.
  • AXI4 user signals cannot be exercised. If exercised, the behavior is undefined.