DPLL Next To HDIO Bank Is Not Supported

Versal AI Core Series Production Errata (EN313)

Document ID
EN313
Release Date
2022-10-21
Revision
1.2 English

Xilinx Answer 72878

The DPLL next to each high-density I/O (HDIO) bank is not supported.

This issue will not be fixed for the devices listed in the Errata Summary table.