Xilinx Answer 73147
The Arm architecture states that a separate observer might observe a write to the translation tables at any time after the execution of the instruction that performed that write. However, it also states that the write is only guaranteed to be observable after the execution of a DSB instruction by the PE that executed the instruction that performed the write to the translation tables.
Because of this errata, it is possible for a subsequent memory operation to generate a translation table walk, which might read a stale translation table descriptor before the write of the translation table descriptor being globally observed. This might lead to an unexpected Data Abort or incorrect translation
This is a third-party errata (Arm, Inc. 1387635); this issue will not be fixed.