Clocking
|
DPLL Deskew Function And ZHOLD Mode Are Not Supported
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
|
73167
Will Not Fix
|
DPLL Next To HDIO Bank Is Not Supported
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
|
72878
Will Not Fix
|
Configurable
Logic Block (CLB) |
Control IMUX Registers Are Not Supported
|
All |
76205
Will Not Fix
|
Data IMUX Registers Are Not Supported
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
XCVC1702
XCVC1502
|
76206
|
Configuration and
Readback |
Readback Capture Is Not Supported
|
All |
75743
Will Not Fix
|
Interconnect |
iPorts Generate False Mission Interrupts
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
|
75748
Will Not Fix
|
Interconnect for CCIX
and PCIe (CPM) |
CPM
Interfaces |
CfgWr Request To Put Device Into PPM D3 In Between Posted Writes Can Cause A UR
|
All |
75749
Will Not Fix
|
I/O |
HDIO/MIO: When An Output Is Powered At 3.3V Or 2.5V, A Race Condition Can Exist Between Data And Tristate
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
|
76889
Will Not Fix
|
Platform Management Controller (PMC) |
IPOR Issued After An SRST Causes A Boot Failure
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
XCVC1702
XCVC1502
|
000033669
Will Not Fix
|
Processing
System |
Application Processing Unit (APU) |
Writes To Normal Memory Might Not Be Made Globally Observed In A Finite Amount Of Time When Core Is Actively In Write Streaming Mode
|
All |
75744
Will Not Fix
|
ELR Recorded Incorrectly On Interrupt Taken Between Cryptographic Instructions In A Sequence
|
All |
73134
Will Not Fix
|
Older Load Incorrectly Reporting A Synchronous External Abort Instead Of A Permission Or Domain Fault Due To A Younger Load Detecting A Synchronous External Abort
|
All |
73164
Will Not Fix
|
APU/RPU Might Hang After Power-up If The JTAG TAP Is Not In The Test-Logic-Reset State
|
XCVC1902
XQVC1902
XQRVC1902
XCVC1802
|
73169
Will Not Fix
|
Trace On Packets From ETM Are Not Generated In Specific Conditions Around System Error Exceptions
|
All |
73146
Will Not Fix
|
DSB Is Insufficient To Ensure Translation Table Entries Being Validated Are Visible To Subsequent Translations
|
All |
73147
Will Not Fix
|
Exception Packet For Return Stack Match Might Return Incorrect [E1:E0] Field
|
All |
73148
Will Not Fix
|
Speculative TLB Fills Might Occur Past A DSB Instruction
|
All |
73149
Will Not Fix
|
An External Data Snoop Might Cause Data Corruption When An Evict Transaction Is Pending
|
All |
73150
Will Not Fix
|
ATB Stall From Trace Subsystem Might Deadlock The Processor
|
All |
73152
Will Not Fix
|
Younger Load Incorrectly Reports A Synchronous External Abort Due To An Older Load Detecting An Asynchronous External Abort
|
All |
72881
Will Not Fix
|
TLBI Does Not Treat Upper ASID Bits As Zero When TCR_EL1.AS Is 0
|
All |
73153
Will Not Fix
|
Persistent Evictions Combined With Interconnect Backpressure Might Stall Write-Back No-Allocate Stores
|
All |
73151
Will Not Fix
|
Speculative AT Instruction Using Out-Of-Context Translation Regime Could Cause Subsequent Request To Generate Incorrect Translation
|
All |
72824
Will Not Fix
|
Speculative Instruction Prefetch To Execute-Never (XN) Memory Can Cause Deadlock Or Data Integrity Issue (Cortex-A72)
|
All |
72836
Will Not Fix
|
Gigabit
Ethernet MAC (GEM) |
GEM Controller Can Trigger Erroneous Amba_Error With Large Send Offload Configuration
|
All |
75745
Will Not Fix
|
PS
Debug and Trace |
AXI Switch CoreSight Management Registers Default to Unlocked
|
All |
72877
Will Not Fix
|
Real-Time Processing Unit (RPU) |
Debug Register DBGDRAR is Set to Incorrect Value
|
All |
76203
Will Not Fix
|
Debug Registers DBGDSAR Are Set To Incorrect Values
|
All |
76204
Will Not Fix
|
Watchpointed Access In A Store Multiple Is Not Masked
|
All |
73161
Will Not Fix
|
Self-Modifying Code In Non-Cacheable Memory Might Not Work With A Slow Memory System
|
All |
73139
Will Not Fix
|
Processor Might Deadlock Or Lose Data
|
All |
73140
Will Not Fix
|