Processing System

Versal AI Core Series Production Errata (EN313)

Document ID: EN313
Release Date: 2023-09-05
Revision: 1.5 English

Introduction
Devices
Errata Summary
Clocking
Calibrated Deskew Is Not Supported
DPLL Deskew Function And ZHOLD Mode Are Not Supported
DPLL Next To HDIO Bank Is Not Supported
Configurable Logic Block (CLB)
Data IMUX Registers Are Not Supported
Interconnect
iPorts Generate False Mission Interrupts
Interconnect for CCIX and PCIe (CPM)
CPM Interfaces
In RC Mode With SMMU Enabled, CCI Transaction Ordering Is Not Followed Between Different Shareability Domain Memories That Have Same AXI ID
In RP Mode, Some Extended Capabilities End At AER
CfgWr Request To Put Device Into PPM D3 In Between Posted Writes Can Cause A UR
I/O
HDIO/MIO: When An Output Is Powered At 3.3V Or 2.5V, A Race Condition Can Exist Between Data And Tristate
Platform Management Controller (PMC)
Primary Boot Is Not Supported With eMMC Devices That Require CMD6 Busy Time Greater Than 1 ms
IPOR Issued After An SRST Causes A Boot Failure
Processing System
Application Processing Unit (APU)
Writes To Normal Memory Might Not Be Made Globally Observed In A Finite Amount Of Time When Core Is Actively In Write Streaming Mode
ELR Recorded Incorrectly On Interrupt Taken Between Cryptographic Instructions In A Sequence
Older Load Incorrectly Reporting A Synchronous External Abort Instead Of A Permission Or Domain Fault Due To A Younger Load Detecting A Synchronous External Abort
APU/RPU Might Hang After Power-up If The JTAG TAP Is Not In The Test-Logic-Reset State
Trace On Packets From ETM Are Not Generated In Specific Conditions Around System Error Exceptions
DSB Is Insufficient To Ensure Translation Table Entries Being Validated Are Visible To Subsequent Translations
Exception Packet For Return Stack Match Might Return Incorrect [E1:E0] Field
Speculative TLB Fills Might Occur Past A DSB Instruction
An External Data Snoop Might Cause Data Corruption When An Evict Transaction Is Pending
ATB Stall From Trace Subsystem Might Deadlock The Processor
Younger Load Incorrectly Reports A Synchronous External Abort Due To An Older Load Detecting An Asynchronous External Abort
TLBI Does Not Treat Upper ASID Bits As Zero When TCR_EL1.AS Is 0
Persistent Evictions Combined With Interconnect Backpressure Might Stall Write-Back No-Allocate Stores
Speculative AT Instruction Using Out-Of-Context Translation Regime Could Cause Subsequent Request To Generate Incorrect Translation
Speculative Instruction Prefetch To Execute-Never (XN) Memory Can Cause Deadlock Or Data Integrity Issue (Cortex-A72)
Gigabit Ethernet MAC (GEM)
GEM Controller Can Trigger Erroneous Amba_Error With Large Send Offload Configuration
PS Debug and Trace
AXI Switch CoreSight Management Registers Default to Unlocked
Real-Time Processing Unit (RPU)
Debug Register DBGDRAR is Set to Incorrect Value
Debug Registers DBGDSAR Are Set To Incorrect Values
Watchpointed Access In A Store Multiple Is Not Masked
Self-Modifying Code In Non-Cacheable Memory Might Not Work With A Slow Memory System
Processor Might Deadlock Or Lose Data
Design Tool Requirements and Guidelines
Traceability
Revision History
Please Read: Important Legal Notices

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