AMD Answer 73140
The Arm Cortex-R5F processor contains a 4-entry store buffer that buffers, merges, and forwards data before it is written to the cache or the L2 memory system using the AXI-master interface. Because of this errata, it is possible for the store buffer to enter a state in which no existing writes will proceed. The effect of this state is either:
- The pipeline backs-up preventing any instruction execution, or
- If a specific sequence of accesses is performed, execution resumes but write data is lost.
This is a third-party errata (Arm, Inc. 780125); this issue will not be fixed.