Xilinx Answer 73161
The Arm Cortex®-R5F processor implements synchronous watchpoints. A synchronous watchpoint generated during a store multiple instruction must ensure that the watchpointed access does not perform writes on the bus to update memory. Because of this errata, this requirement is not met and the processor incorrectly updates memory for a watchpointed access.
This is a third-party errata (Arm, Inc. 756523); this issue will not be fixed.